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[test] update golden for device1x1 no time stamp netlists

This commit is contained in:
tangxifan 2022-11-03 17:48:40 -07:00
parent 55e99a7de4
commit 5f74367c2e
8 changed files with 449 additions and 474 deletions
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4
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v
View File

@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb;
initial begin initial begin
clk[0] <= 1'b0; clk[0] <= 1'b0;
while(1) begin while(1) begin
#0.5744515657 #0.7626540661
clk[0] <= !clk[0]; clk[0] <= !clk[0];
end end
end end
@ -109,7 +109,7 @@ initial begin
$timeformat(-9, 2, "ns", 20); $timeformat(-9, 2, "ns", 20);
$display("Simulation start"); $display("Simulation start");
// ----- Can be changed by the user for his/her need ------- // ----- Can be changed by the user for his/her need -------
#8.042322159 #10.6771574
if(nb_error == 0) begin if(nb_error == 0) begin
$display("Simulation Succeed"); $display("Simulation Succeed");
end else begin end else begin

197
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc
View File

@ -9,14 +9,14 @@
################################################## ##################################################
# Create clock # Create clock
################################################## ##################################################
create_clock clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} create_clock clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10}
################################################## ##################################################
# Create input and output delays for used I/Os # Create input and output delays for used I/Os
################################################## ##################################################
set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[26] set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[27]
set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[25] set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[15]
set_output_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[11] set_output_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[12]
################################################## ##################################################
# Disable timing for unused I/Os # Disable timing for unused I/Os
@ -32,10 +32,9 @@ set_disable_timing gfpga_pad_GPIO_PAD[7]
set_disable_timing gfpga_pad_GPIO_PAD[8] set_disable_timing gfpga_pad_GPIO_PAD[8]
set_disable_timing gfpga_pad_GPIO_PAD[9] set_disable_timing gfpga_pad_GPIO_PAD[9]
set_disable_timing gfpga_pad_GPIO_PAD[10] set_disable_timing gfpga_pad_GPIO_PAD[10]
set_disable_timing gfpga_pad_GPIO_PAD[12] set_disable_timing gfpga_pad_GPIO_PAD[11]
set_disable_timing gfpga_pad_GPIO_PAD[13] set_disable_timing gfpga_pad_GPIO_PAD[13]
set_disable_timing gfpga_pad_GPIO_PAD[14] set_disable_timing gfpga_pad_GPIO_PAD[14]
set_disable_timing gfpga_pad_GPIO_PAD[15]
set_disable_timing gfpga_pad_GPIO_PAD[16] set_disable_timing gfpga_pad_GPIO_PAD[16]
set_disable_timing gfpga_pad_GPIO_PAD[17] set_disable_timing gfpga_pad_GPIO_PAD[17]
set_disable_timing gfpga_pad_GPIO_PAD[18] set_disable_timing gfpga_pad_GPIO_PAD[18]
@ -45,7 +44,8 @@ set_disable_timing gfpga_pad_GPIO_PAD[21]
set_disable_timing gfpga_pad_GPIO_PAD[22] set_disable_timing gfpga_pad_GPIO_PAD[22]
set_disable_timing gfpga_pad_GPIO_PAD[23] set_disable_timing gfpga_pad_GPIO_PAD[23]
set_disable_timing gfpga_pad_GPIO_PAD[24] set_disable_timing gfpga_pad_GPIO_PAD[24]
set_disable_timing gfpga_pad_GPIO_PAD[27] set_disable_timing gfpga_pad_GPIO_PAD[25]
set_disable_timing gfpga_pad_GPIO_PAD[26]
set_disable_timing gfpga_pad_GPIO_PAD[28] set_disable_timing gfpga_pad_GPIO_PAD[28]
set_disable_timing gfpga_pad_GPIO_PAD[29] set_disable_timing gfpga_pad_GPIO_PAD[29]
set_disable_timing gfpga_pad_GPIO_PAD[30] set_disable_timing gfpga_pad_GPIO_PAD[30]
@ -156,7 +156,6 @@ set_disable_timing cbx_1__0_/chanx_left_in[7]
set_disable_timing cbx_1__0_/chanx_right_in[7] set_disable_timing cbx_1__0_/chanx_right_in[7]
set_disable_timing cbx_1__0_/chanx_left_in[8] set_disable_timing cbx_1__0_/chanx_left_in[8]
set_disable_timing cbx_1__0_/chanx_right_in[8] set_disable_timing cbx_1__0_/chanx_right_in[8]
set_disable_timing cbx_1__0_/chanx_left_in[9]
set_disable_timing cbx_1__0_/chanx_right_in[9] set_disable_timing cbx_1__0_/chanx_right_in[9]
set_disable_timing cbx_1__0_/chanx_left_in[10] set_disable_timing cbx_1__0_/chanx_left_in[10]
set_disable_timing cbx_1__0_/chanx_right_in[10] set_disable_timing cbx_1__0_/chanx_right_in[10]
@ -181,7 +180,6 @@ set_disable_timing cbx_1__0_/chanx_left_out[7]
set_disable_timing cbx_1__0_/chanx_right_out[7] set_disable_timing cbx_1__0_/chanx_right_out[7]
set_disable_timing cbx_1__0_/chanx_left_out[8] set_disable_timing cbx_1__0_/chanx_left_out[8]
set_disable_timing cbx_1__0_/chanx_right_out[8] set_disable_timing cbx_1__0_/chanx_right_out[8]
set_disable_timing cbx_1__0_/chanx_left_out[9]
set_disable_timing cbx_1__0_/chanx_right_out[9] set_disable_timing cbx_1__0_/chanx_right_out[9]
set_disable_timing cbx_1__0_/chanx_left_out[10] set_disable_timing cbx_1__0_/chanx_left_out[10]
set_disable_timing cbx_1__0_/chanx_right_out[10] set_disable_timing cbx_1__0_/chanx_right_out[10]
@ -274,7 +272,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[1]
set_disable_timing cbx_1__1_/chanx_left_in[2] set_disable_timing cbx_1__1_/chanx_left_in[2]
set_disable_timing cbx_1__1_/chanx_right_in[2] set_disable_timing cbx_1__1_/chanx_right_in[2]
set_disable_timing cbx_1__1_/chanx_left_in[3] set_disable_timing cbx_1__1_/chanx_left_in[3]
set_disable_timing cbx_1__1_/chanx_right_in[3]
set_disable_timing cbx_1__1_/chanx_left_in[4] set_disable_timing cbx_1__1_/chanx_left_in[4]
set_disable_timing cbx_1__1_/chanx_right_in[4] set_disable_timing cbx_1__1_/chanx_right_in[4]
set_disable_timing cbx_1__1_/chanx_left_in[5] set_disable_timing cbx_1__1_/chanx_left_in[5]
@ -283,7 +280,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[6]
set_disable_timing cbx_1__1_/chanx_right_in[6] set_disable_timing cbx_1__1_/chanx_right_in[6]
set_disable_timing cbx_1__1_/chanx_left_in[7] set_disable_timing cbx_1__1_/chanx_left_in[7]
set_disable_timing cbx_1__1_/chanx_right_in[7] set_disable_timing cbx_1__1_/chanx_right_in[7]
set_disable_timing cbx_1__1_/chanx_left_in[8]
set_disable_timing cbx_1__1_/chanx_right_in[8] set_disable_timing cbx_1__1_/chanx_right_in[8]
set_disable_timing cbx_1__1_/chanx_left_in[9] set_disable_timing cbx_1__1_/chanx_left_in[9]
set_disable_timing cbx_1__1_/chanx_right_in[9] set_disable_timing cbx_1__1_/chanx_right_in[9]
@ -299,7 +295,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[1]
set_disable_timing cbx_1__1_/chanx_left_out[2] set_disable_timing cbx_1__1_/chanx_left_out[2]
set_disable_timing cbx_1__1_/chanx_right_out[2] set_disable_timing cbx_1__1_/chanx_right_out[2]
set_disable_timing cbx_1__1_/chanx_left_out[3] set_disable_timing cbx_1__1_/chanx_left_out[3]
set_disable_timing cbx_1__1_/chanx_right_out[3]
set_disable_timing cbx_1__1_/chanx_left_out[4] set_disable_timing cbx_1__1_/chanx_left_out[4]
set_disable_timing cbx_1__1_/chanx_right_out[4] set_disable_timing cbx_1__1_/chanx_right_out[4]
set_disable_timing cbx_1__1_/chanx_left_out[5] set_disable_timing cbx_1__1_/chanx_left_out[5]
@ -308,7 +303,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[6]
set_disable_timing cbx_1__1_/chanx_right_out[6] set_disable_timing cbx_1__1_/chanx_right_out[6]
set_disable_timing cbx_1__1_/chanx_left_out[7] set_disable_timing cbx_1__1_/chanx_left_out[7]
set_disable_timing cbx_1__1_/chanx_right_out[7] set_disable_timing cbx_1__1_/chanx_right_out[7]
set_disable_timing cbx_1__1_/chanx_left_out[8]
set_disable_timing cbx_1__1_/chanx_right_out[8] set_disable_timing cbx_1__1_/chanx_right_out[8]
set_disable_timing cbx_1__1_/chanx_left_out[9] set_disable_timing cbx_1__1_/chanx_left_out[9]
set_disable_timing cbx_1__1_/chanx_right_out[9] set_disable_timing cbx_1__1_/chanx_right_out[9]
@ -326,7 +320,6 @@ set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_out
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0]
set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0]
set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1] set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1]
@ -374,7 +367,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4]
set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4] set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5]
set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3] set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3]
set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4]
set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4]
@ -398,11 +390,12 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4]
################################################## ##################################################
# Disable timing for Connection block cby_0__1_ # Disable timing for Connection block cby_0__1_
################################################## ##################################################
set_disable_timing cby_0__1_/chany_bottom_in[0]
set_disable_timing cby_0__1_/chany_top_in[0] set_disable_timing cby_0__1_/chany_top_in[0]
set_disable_timing cby_0__1_/chany_bottom_in[1]
set_disable_timing cby_0__1_/chany_top_in[1] set_disable_timing cby_0__1_/chany_top_in[1]
set_disable_timing cby_0__1_/chany_bottom_in[2] set_disable_timing cby_0__1_/chany_bottom_in[2]
set_disable_timing cby_0__1_/chany_top_in[2] set_disable_timing cby_0__1_/chany_top_in[2]
set_disable_timing cby_0__1_/chany_bottom_in[3]
set_disable_timing cby_0__1_/chany_top_in[3] set_disable_timing cby_0__1_/chany_top_in[3]
set_disable_timing cby_0__1_/chany_bottom_in[4] set_disable_timing cby_0__1_/chany_bottom_in[4]
set_disable_timing cby_0__1_/chany_top_in[4] set_disable_timing cby_0__1_/chany_top_in[4]
@ -413,7 +406,6 @@ set_disable_timing cby_0__1_/chany_top_in[6]
set_disable_timing cby_0__1_/chany_bottom_in[7] set_disable_timing cby_0__1_/chany_bottom_in[7]
set_disable_timing cby_0__1_/chany_top_in[7] set_disable_timing cby_0__1_/chany_top_in[7]
set_disable_timing cby_0__1_/chany_bottom_in[8] set_disable_timing cby_0__1_/chany_bottom_in[8]
set_disable_timing cby_0__1_/chany_top_in[8]
set_disable_timing cby_0__1_/chany_bottom_in[9] set_disable_timing cby_0__1_/chany_bottom_in[9]
set_disable_timing cby_0__1_/chany_top_in[9] set_disable_timing cby_0__1_/chany_top_in[9]
set_disable_timing cby_0__1_/chany_bottom_in[10] set_disable_timing cby_0__1_/chany_bottom_in[10]
@ -421,11 +413,12 @@ set_disable_timing cby_0__1_/chany_bottom_in[11]
set_disable_timing cby_0__1_/chany_top_in[11] set_disable_timing cby_0__1_/chany_top_in[11]
set_disable_timing cby_0__1_/chany_bottom_in[12] set_disable_timing cby_0__1_/chany_bottom_in[12]
set_disable_timing cby_0__1_/chany_top_in[12] set_disable_timing cby_0__1_/chany_top_in[12]
set_disable_timing cby_0__1_/chany_bottom_out[0]
set_disable_timing cby_0__1_/chany_top_out[0] set_disable_timing cby_0__1_/chany_top_out[0]
set_disable_timing cby_0__1_/chany_bottom_out[1]
set_disable_timing cby_0__1_/chany_top_out[1] set_disable_timing cby_0__1_/chany_top_out[1]
set_disable_timing cby_0__1_/chany_bottom_out[2] set_disable_timing cby_0__1_/chany_bottom_out[2]
set_disable_timing cby_0__1_/chany_top_out[2] set_disable_timing cby_0__1_/chany_top_out[2]
set_disable_timing cby_0__1_/chany_bottom_out[3]
set_disable_timing cby_0__1_/chany_top_out[3] set_disable_timing cby_0__1_/chany_top_out[3]
set_disable_timing cby_0__1_/chany_bottom_out[4] set_disable_timing cby_0__1_/chany_bottom_out[4]
set_disable_timing cby_0__1_/chany_top_out[4] set_disable_timing cby_0__1_/chany_top_out[4]
@ -436,7 +429,6 @@ set_disable_timing cby_0__1_/chany_top_out[6]
set_disable_timing cby_0__1_/chany_bottom_out[7] set_disable_timing cby_0__1_/chany_bottom_out[7]
set_disable_timing cby_0__1_/chany_top_out[7] set_disable_timing cby_0__1_/chany_top_out[7]
set_disable_timing cby_0__1_/chany_bottom_out[8] set_disable_timing cby_0__1_/chany_bottom_out[8]
set_disable_timing cby_0__1_/chany_top_out[8]
set_disable_timing cby_0__1_/chany_bottom_out[9] set_disable_timing cby_0__1_/chany_bottom_out[9]
set_disable_timing cby_0__1_/chany_top_out[9] set_disable_timing cby_0__1_/chany_top_out[9]
set_disable_timing cby_0__1_/chany_bottom_out[10] set_disable_timing cby_0__1_/chany_bottom_out[10]
@ -444,6 +436,8 @@ set_disable_timing cby_0__1_/chany_bottom_out[11]
set_disable_timing cby_0__1_/chany_top_out[11] set_disable_timing cby_0__1_/chany_top_out[11]
set_disable_timing cby_0__1_/chany_bottom_out[12] set_disable_timing cby_0__1_/chany_bottom_out[12]
set_disable_timing cby_0__1_/chany_top_out[12] set_disable_timing cby_0__1_/chany_top_out[12]
set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0]
set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0]
@ -452,11 +446,13 @@ set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_out
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0]
set_disable_timing cby_0__1_/mux_left_ipin_0/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[1] set_disable_timing cby_0__1_/mux_left_ipin_1/in[1]
set_disable_timing cby_0__1_/mux_right_ipin_5/in[1] set_disable_timing cby_0__1_/mux_right_ipin_5/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_0/in[0] set_disable_timing cby_0__1_/mux_left_ipin_0/in[0]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[0] set_disable_timing cby_0__1_/mux_left_ipin_1/in[0]
set_disable_timing cby_0__1_/mux_right_ipin_5/in[0] set_disable_timing cby_0__1_/mux_right_ipin_5/in[0]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[3]
set_disable_timing cby_0__1_/mux_right_ipin_0/in[1] set_disable_timing cby_0__1_/mux_right_ipin_0/in[1]
set_disable_timing cby_0__1_/mux_right_ipin_6/in[1] set_disable_timing cby_0__1_/mux_right_ipin_6/in[1]
set_disable_timing cby_0__1_/mux_left_ipin_1/in[2] set_disable_timing cby_0__1_/mux_left_ipin_1/in[2]
@ -514,12 +510,10 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4]
# Disable timing for Connection block cby_1__1_ # Disable timing for Connection block cby_1__1_
################################################## ##################################################
set_disable_timing cby_1__1_/chany_top_in[0] set_disable_timing cby_1__1_/chany_top_in[0]
set_disable_timing cby_1__1_/chany_bottom_in[1]
set_disable_timing cby_1__1_/chany_top_in[1] set_disable_timing cby_1__1_/chany_top_in[1]
set_disable_timing cby_1__1_/chany_top_in[2] set_disable_timing cby_1__1_/chany_top_in[2]
set_disable_timing cby_1__1_/chany_bottom_in[3] set_disable_timing cby_1__1_/chany_bottom_in[3]
set_disable_timing cby_1__1_/chany_top_in[3] set_disable_timing cby_1__1_/chany_top_in[3]
set_disable_timing cby_1__1_/chany_bottom_in[4]
set_disable_timing cby_1__1_/chany_top_in[4] set_disable_timing cby_1__1_/chany_top_in[4]
set_disable_timing cby_1__1_/chany_bottom_in[5] set_disable_timing cby_1__1_/chany_bottom_in[5]
set_disable_timing cby_1__1_/chany_top_in[5] set_disable_timing cby_1__1_/chany_top_in[5]
@ -538,12 +532,10 @@ set_disable_timing cby_1__1_/chany_top_in[11]
set_disable_timing cby_1__1_/chany_bottom_in[12] set_disable_timing cby_1__1_/chany_bottom_in[12]
set_disable_timing cby_1__1_/chany_top_in[12] set_disable_timing cby_1__1_/chany_top_in[12]
set_disable_timing cby_1__1_/chany_top_out[0] set_disable_timing cby_1__1_/chany_top_out[0]
set_disable_timing cby_1__1_/chany_bottom_out[1]
set_disable_timing cby_1__1_/chany_top_out[1] set_disable_timing cby_1__1_/chany_top_out[1]
set_disable_timing cby_1__1_/chany_top_out[2] set_disable_timing cby_1__1_/chany_top_out[2]
set_disable_timing cby_1__1_/chany_bottom_out[3] set_disable_timing cby_1__1_/chany_bottom_out[3]
set_disable_timing cby_1__1_/chany_top_out[3] set_disable_timing cby_1__1_/chany_top_out[3]
set_disable_timing cby_1__1_/chany_bottom_out[4]
set_disable_timing cby_1__1_/chany_top_out[4] set_disable_timing cby_1__1_/chany_top_out[4]
set_disable_timing cby_1__1_/chany_bottom_out[5] set_disable_timing cby_1__1_/chany_bottom_out[5]
set_disable_timing cby_1__1_/chany_top_out[5] set_disable_timing cby_1__1_/chany_top_out[5]
@ -564,11 +556,10 @@ set_disable_timing cby_1__1_/chany_top_out[12]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0]
set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0]
set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0]
set_disable_timing cby_1__1_/mux_left_ipin_0/in[1] set_disable_timing cby_1__1_/mux_left_ipin_0/in[1]
@ -579,11 +570,11 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_7/in[0] set_disable_timing cby_1__1_/mux_left_ipin_7/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[3] set_disable_timing cby_1__1_/mux_left_ipin_1/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[1] set_disable_timing cby_1__1_/mux_left_ipin_2/in[1]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_1/in[2] set_disable_timing cby_1__1_/mux_left_ipin_1/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[0] set_disable_timing cby_1__1_/mux_left_ipin_2/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_0/in[0] set_disable_timing cby_1__1_/mux_right_ipin_0/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[3] set_disable_timing cby_1__1_/mux_left_ipin_2/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[1]
set_disable_timing cby_1__1_/mux_right_ipin_1/in[1] set_disable_timing cby_1__1_/mux_right_ipin_1/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_2/in[2] set_disable_timing cby_1__1_/mux_left_ipin_2/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[0] set_disable_timing cby_1__1_/mux_left_ipin_3/in[0]
@ -594,7 +585,6 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] set_disable_timing cby_1__1_/mux_left_ipin_3/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] set_disable_timing cby_1__1_/mux_left_ipin_4/in[0]
set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] set_disable_timing cby_1__1_/mux_right_ipin_2/in[0]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[3]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] set_disable_timing cby_1__1_/mux_left_ipin_5/in[1]
set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] set_disable_timing cby_1__1_/mux_left_ipin_4/in[2]
set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] set_disable_timing cby_1__1_/mux_left_ipin_5/in[0]
@ -639,11 +629,12 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[4]
################################################## ##################################################
# Disable timing for Switch block sb_0__0_ # Disable timing for Switch block sb_0__0_
################################################## ##################################################
set_disable_timing sb_0__0_/chany_top_out[0]
set_disable_timing sb_0__0_/chany_top_in[0] set_disable_timing sb_0__0_/chany_top_in[0]
set_disable_timing sb_0__0_/chany_top_out[1]
set_disable_timing sb_0__0_/chany_top_in[1] set_disable_timing sb_0__0_/chany_top_in[1]
set_disable_timing sb_0__0_/chany_top_out[2] set_disable_timing sb_0__0_/chany_top_out[2]
set_disable_timing sb_0__0_/chany_top_in[2] set_disable_timing sb_0__0_/chany_top_in[2]
set_disable_timing sb_0__0_/chany_top_out[3]
set_disable_timing sb_0__0_/chany_top_in[3] set_disable_timing sb_0__0_/chany_top_in[3]
set_disable_timing sb_0__0_/chany_top_out[4] set_disable_timing sb_0__0_/chany_top_out[4]
set_disable_timing sb_0__0_/chany_top_in[4] set_disable_timing sb_0__0_/chany_top_in[4]
@ -654,7 +645,6 @@ set_disable_timing sb_0__0_/chany_top_in[6]
set_disable_timing sb_0__0_/chany_top_out[7] set_disable_timing sb_0__0_/chany_top_out[7]
set_disable_timing sb_0__0_/chany_top_in[7] set_disable_timing sb_0__0_/chany_top_in[7]
set_disable_timing sb_0__0_/chany_top_out[8] set_disable_timing sb_0__0_/chany_top_out[8]
set_disable_timing sb_0__0_/chany_top_in[8]
set_disable_timing sb_0__0_/chany_top_out[9] set_disable_timing sb_0__0_/chany_top_out[9]
set_disable_timing sb_0__0_/chany_top_in[9] set_disable_timing sb_0__0_/chany_top_in[9]
set_disable_timing sb_0__0_/chany_top_out[10] set_disable_timing sb_0__0_/chany_top_out[10]
@ -680,7 +670,6 @@ set_disable_timing sb_0__0_/chanx_right_out[7]
set_disable_timing sb_0__0_/chanx_right_in[7] set_disable_timing sb_0__0_/chanx_right_in[7]
set_disable_timing sb_0__0_/chanx_right_out[8] set_disable_timing sb_0__0_/chanx_right_out[8]
set_disable_timing sb_0__0_/chanx_right_in[8] set_disable_timing sb_0__0_/chanx_right_in[8]
set_disable_timing sb_0__0_/chanx_right_out[9]
set_disable_timing sb_0__0_/chanx_right_in[9] set_disable_timing sb_0__0_/chanx_right_in[9]
set_disable_timing sb_0__0_/chanx_right_out[10] set_disable_timing sb_0__0_/chanx_right_out[10]
set_disable_timing sb_0__0_/chanx_right_in[10] set_disable_timing sb_0__0_/chanx_right_in[10]
@ -688,7 +677,8 @@ set_disable_timing sb_0__0_/chanx_right_in[11]
set_disable_timing sb_0__0_/chanx_right_out[12] set_disable_timing sb_0__0_/chanx_right_out[12]
set_disable_timing sb_0__0_/chanx_right_in[12] set_disable_timing sb_0__0_/chanx_right_in[12]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@ -706,12 +696,13 @@ set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi
set_disable_timing sb_0__0_/mux_top_track_0/in[0] set_disable_timing sb_0__0_/mux_top_track_0/in[0]
set_disable_timing sb_0__0_/mux_top_track_12/in[0] set_disable_timing sb_0__0_/mux_top_track_12/in[0]
set_disable_timing sb_0__0_/mux_top_track_24/in[0] set_disable_timing sb_0__0_/mux_top_track_24/in[0]
set_disable_timing sb_0__0_/mux_top_track_0/in[1]
set_disable_timing sb_0__0_/mux_top_track_2/in[0] set_disable_timing sb_0__0_/mux_top_track_2/in[0]
set_disable_timing sb_0__0_/mux_top_track_14/in[0] set_disable_timing sb_0__0_/mux_top_track_14/in[0]
set_disable_timing sb_0__0_/mux_top_track_2/in[1]
set_disable_timing sb_0__0_/mux_top_track_4/in[0] set_disable_timing sb_0__0_/mux_top_track_4/in[0]
set_disable_timing sb_0__0_/mux_top_track_16/in[0] set_disable_timing sb_0__0_/mux_top_track_16/in[0]
set_disable_timing sb_0__0_/mux_top_track_4/in[1] set_disable_timing sb_0__0_/mux_top_track_4/in[1]
set_disable_timing sb_0__0_/mux_top_track_6/in[0]
set_disable_timing sb_0__0_/mux_top_track_18/in[0] set_disable_timing sb_0__0_/mux_top_track_18/in[0]
set_disable_timing sb_0__0_/mux_top_track_6/in[1] set_disable_timing sb_0__0_/mux_top_track_6/in[1]
set_disable_timing sb_0__0_/mux_top_track_8/in[0] set_disable_timing sb_0__0_/mux_top_track_8/in[0]
@ -761,7 +752,6 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0]
set_disable_timing sb_0__0_/mux_right_track_12/in[0] set_disable_timing sb_0__0_/mux_right_track_12/in[0]
set_disable_timing sb_0__0_/mux_right_track_14/in[0] set_disable_timing sb_0__0_/mux_right_track_14/in[0]
set_disable_timing sb_0__0_/mux_right_track_16/in[0] set_disable_timing sb_0__0_/mux_right_track_16/in[0]
set_disable_timing sb_0__0_/mux_right_track_18/in[0]
set_disable_timing sb_0__0_/mux_right_track_20/in[0] set_disable_timing sb_0__0_/mux_right_track_20/in[0]
set_disable_timing sb_0__0_/mux_right_track_24/in[0] set_disable_timing sb_0__0_/mux_right_track_24/in[0]
set_disable_timing sb_0__0_/mux_right_track_0/in[0] set_disable_timing sb_0__0_/mux_right_track_0/in[0]
@ -787,7 +777,6 @@ set_disable_timing sb_0__1_/chanx_right_out[1]
set_disable_timing sb_0__1_/chanx_right_out[2] set_disable_timing sb_0__1_/chanx_right_out[2]
set_disable_timing sb_0__1_/chanx_right_in[2] set_disable_timing sb_0__1_/chanx_right_in[2]
set_disable_timing sb_0__1_/chanx_right_out[3] set_disable_timing sb_0__1_/chanx_right_out[3]
set_disable_timing sb_0__1_/chanx_right_in[3]
set_disable_timing sb_0__1_/chanx_right_out[4] set_disable_timing sb_0__1_/chanx_right_out[4]
set_disable_timing sb_0__1_/chanx_right_in[4] set_disable_timing sb_0__1_/chanx_right_in[4]
set_disable_timing sb_0__1_/chanx_right_out[5] set_disable_timing sb_0__1_/chanx_right_out[5]
@ -796,7 +785,6 @@ set_disable_timing sb_0__1_/chanx_right_out[6]
set_disable_timing sb_0__1_/chanx_right_in[6] set_disable_timing sb_0__1_/chanx_right_in[6]
set_disable_timing sb_0__1_/chanx_right_out[7] set_disable_timing sb_0__1_/chanx_right_out[7]
set_disable_timing sb_0__1_/chanx_right_in[7] set_disable_timing sb_0__1_/chanx_right_in[7]
set_disable_timing sb_0__1_/chanx_right_out[8]
set_disable_timing sb_0__1_/chanx_right_in[8] set_disable_timing sb_0__1_/chanx_right_in[8]
set_disable_timing sb_0__1_/chanx_right_out[9] set_disable_timing sb_0__1_/chanx_right_out[9]
set_disable_timing sb_0__1_/chanx_right_in[9] set_disable_timing sb_0__1_/chanx_right_in[9]
@ -806,11 +794,12 @@ set_disable_timing sb_0__1_/chanx_right_out[11]
set_disable_timing sb_0__1_/chanx_right_in[11] set_disable_timing sb_0__1_/chanx_right_in[11]
set_disable_timing sb_0__1_/chanx_right_out[12] set_disable_timing sb_0__1_/chanx_right_out[12]
set_disable_timing sb_0__1_/chanx_right_in[12] set_disable_timing sb_0__1_/chanx_right_in[12]
set_disable_timing sb_0__1_/chany_bottom_in[0]
set_disable_timing sb_0__1_/chany_bottom_out[0] set_disable_timing sb_0__1_/chany_bottom_out[0]
set_disable_timing sb_0__1_/chany_bottom_in[1]
set_disable_timing sb_0__1_/chany_bottom_out[1] set_disable_timing sb_0__1_/chany_bottom_out[1]
set_disable_timing sb_0__1_/chany_bottom_in[2] set_disable_timing sb_0__1_/chany_bottom_in[2]
set_disable_timing sb_0__1_/chany_bottom_out[2] set_disable_timing sb_0__1_/chany_bottom_out[2]
set_disable_timing sb_0__1_/chany_bottom_in[3]
set_disable_timing sb_0__1_/chany_bottom_out[3] set_disable_timing sb_0__1_/chany_bottom_out[3]
set_disable_timing sb_0__1_/chany_bottom_in[4] set_disable_timing sb_0__1_/chany_bottom_in[4]
set_disable_timing sb_0__1_/chany_bottom_out[4] set_disable_timing sb_0__1_/chany_bottom_out[4]
@ -821,7 +810,6 @@ set_disable_timing sb_0__1_/chany_bottom_out[6]
set_disable_timing sb_0__1_/chany_bottom_in[7] set_disable_timing sb_0__1_/chany_bottom_in[7]
set_disable_timing sb_0__1_/chany_bottom_out[7] set_disable_timing sb_0__1_/chany_bottom_out[7]
set_disable_timing sb_0__1_/chany_bottom_in[8] set_disable_timing sb_0__1_/chany_bottom_in[8]
set_disable_timing sb_0__1_/chany_bottom_out[8]
set_disable_timing sb_0__1_/chany_bottom_in[9] set_disable_timing sb_0__1_/chany_bottom_in[9]
set_disable_timing sb_0__1_/chany_bottom_out[9] set_disable_timing sb_0__1_/chany_bottom_out[9]
set_disable_timing sb_0__1_/chany_bottom_in[10] set_disable_timing sb_0__1_/chany_bottom_in[10]
@ -840,7 +828,8 @@ set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pi
set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0]
set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0]
@ -897,7 +886,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_15/in[3]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] set_disable_timing sb_0__1_/mux_bottom_track_17/in[2]
set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] set_disable_timing sb_0__1_/mux_bottom_track_23/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] set_disable_timing sb_0__1_/mux_bottom_track_19/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_17/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] set_disable_timing sb_0__1_/mux_bottom_track_15/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] set_disable_timing sb_0__1_/mux_bottom_track_13/in[0]
set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] set_disable_timing sb_0__1_/mux_bottom_track_11/in[0]
@ -910,7 +898,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_25/in[0]
set_disable_timing sb_0__1_/mux_right_track_22/in[1] set_disable_timing sb_0__1_/mux_right_track_22/in[1]
set_disable_timing sb_0__1_/mux_right_track_20/in[1] set_disable_timing sb_0__1_/mux_right_track_20/in[1]
set_disable_timing sb_0__1_/mux_right_track_18/in[1] set_disable_timing sb_0__1_/mux_right_track_18/in[1]
set_disable_timing sb_0__1_/mux_right_track_16/in[2]
set_disable_timing sb_0__1_/mux_right_track_14/in[2] set_disable_timing sb_0__1_/mux_right_track_14/in[2]
set_disable_timing sb_0__1_/mux_right_track_12/in[3] set_disable_timing sb_0__1_/mux_right_track_12/in[3]
set_disable_timing sb_0__1_/mux_right_track_10/in[2] set_disable_timing sb_0__1_/mux_right_track_10/in[2]
@ -924,12 +911,10 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2]
# Disable timing for Switch block sb_1__0_ # Disable timing for Switch block sb_1__0_
################################################## ##################################################
set_disable_timing sb_1__0_/chany_top_in[0] set_disable_timing sb_1__0_/chany_top_in[0]
set_disable_timing sb_1__0_/chany_top_out[1]
set_disable_timing sb_1__0_/chany_top_in[1] set_disable_timing sb_1__0_/chany_top_in[1]
set_disable_timing sb_1__0_/chany_top_in[2] set_disable_timing sb_1__0_/chany_top_in[2]
set_disable_timing sb_1__0_/chany_top_out[3] set_disable_timing sb_1__0_/chany_top_out[3]
set_disable_timing sb_1__0_/chany_top_in[3] set_disable_timing sb_1__0_/chany_top_in[3]
set_disable_timing sb_1__0_/chany_top_out[4]
set_disable_timing sb_1__0_/chany_top_in[4] set_disable_timing sb_1__0_/chany_top_in[4]
set_disable_timing sb_1__0_/chany_top_out[5] set_disable_timing sb_1__0_/chany_top_out[5]
set_disable_timing sb_1__0_/chany_top_in[5] set_disable_timing sb_1__0_/chany_top_in[5]
@ -965,7 +950,6 @@ set_disable_timing sb_1__0_/chanx_left_in[7]
set_disable_timing sb_1__0_/chanx_left_out[7] set_disable_timing sb_1__0_/chanx_left_out[7]
set_disable_timing sb_1__0_/chanx_left_in[8] set_disable_timing sb_1__0_/chanx_left_in[8]
set_disable_timing sb_1__0_/chanx_left_out[8] set_disable_timing sb_1__0_/chanx_left_out[8]
set_disable_timing sb_1__0_/chanx_left_in[9]
set_disable_timing sb_1__0_/chanx_left_out[9] set_disable_timing sb_1__0_/chanx_left_out[9]
set_disable_timing sb_1__0_/chanx_left_in[10] set_disable_timing sb_1__0_/chanx_left_in[10]
set_disable_timing sb_1__0_/chanx_left_out[10] set_disable_timing sb_1__0_/chanx_left_out[10]
@ -979,7 +963,6 @@ set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0]
@ -1010,7 +993,6 @@ set_disable_timing sb_1__0_/mux_top_track_24/in[0]
set_disable_timing sb_1__0_/mux_top_track_0/in[2] set_disable_timing sb_1__0_/mux_top_track_0/in[2]
set_disable_timing sb_1__0_/mux_top_track_12/in[1] set_disable_timing sb_1__0_/mux_top_track_12/in[1]
set_disable_timing sb_1__0_/mux_top_track_14/in[1] set_disable_timing sb_1__0_/mux_top_track_14/in[1]
set_disable_timing sb_1__0_/mux_top_track_2/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[2]
set_disable_timing sb_1__0_/mux_top_track_16/in[1] set_disable_timing sb_1__0_/mux_top_track_16/in[1]
set_disable_timing sb_1__0_/mux_left_track_1/in[1] set_disable_timing sb_1__0_/mux_left_track_1/in[1]
@ -1062,19 +1044,16 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2]
set_disable_timing sb_1__0_/mux_top_track_14/in[3] set_disable_timing sb_1__0_/mux_top_track_14/in[3]
set_disable_timing sb_1__0_/mux_top_track_12/in[2] set_disable_timing sb_1__0_/mux_top_track_12/in[2]
set_disable_timing sb_1__0_/mux_top_track_10/in[2] set_disable_timing sb_1__0_/mux_top_track_10/in[2]
set_disable_timing sb_1__0_/mux_top_track_8/in[2]
set_disable_timing sb_1__0_/mux_top_track_6/in[2] set_disable_timing sb_1__0_/mux_top_track_6/in[2]
set_disable_timing sb_1__0_/mux_top_track_2/in[3] set_disable_timing sb_1__0_/mux_top_track_2/in[3]
################################################## ##################################################
# Disable timing for Switch block sb_1__1_ # Disable timing for Switch block sb_1__1_
################################################## ##################################################
set_disable_timing sb_1__1_/chany_bottom_out[0] set_disable_timing sb_1__1_/chany_bottom_out[0]
set_disable_timing sb_1__1_/chany_bottom_in[1]
set_disable_timing sb_1__1_/chany_bottom_out[1] set_disable_timing sb_1__1_/chany_bottom_out[1]
set_disable_timing sb_1__1_/chany_bottom_out[2] set_disable_timing sb_1__1_/chany_bottom_out[2]
set_disable_timing sb_1__1_/chany_bottom_in[3] set_disable_timing sb_1__1_/chany_bottom_in[3]
set_disable_timing sb_1__1_/chany_bottom_out[3] set_disable_timing sb_1__1_/chany_bottom_out[3]
set_disable_timing sb_1__1_/chany_bottom_in[4]
set_disable_timing sb_1__1_/chany_bottom_out[4] set_disable_timing sb_1__1_/chany_bottom_out[4]
set_disable_timing sb_1__1_/chany_bottom_in[5] set_disable_timing sb_1__1_/chany_bottom_in[5]
set_disable_timing sb_1__1_/chany_bottom_out[5] set_disable_timing sb_1__1_/chany_bottom_out[5]
@ -1098,7 +1077,6 @@ set_disable_timing sb_1__1_/chanx_left_in[1]
set_disable_timing sb_1__1_/chanx_left_in[2] set_disable_timing sb_1__1_/chanx_left_in[2]
set_disable_timing sb_1__1_/chanx_left_out[2] set_disable_timing sb_1__1_/chanx_left_out[2]
set_disable_timing sb_1__1_/chanx_left_in[3] set_disable_timing sb_1__1_/chanx_left_in[3]
set_disable_timing sb_1__1_/chanx_left_out[3]
set_disable_timing sb_1__1_/chanx_left_in[4] set_disable_timing sb_1__1_/chanx_left_in[4]
set_disable_timing sb_1__1_/chanx_left_out[4] set_disable_timing sb_1__1_/chanx_left_out[4]
set_disable_timing sb_1__1_/chanx_left_in[5] set_disable_timing sb_1__1_/chanx_left_in[5]
@ -1107,7 +1085,6 @@ set_disable_timing sb_1__1_/chanx_left_in[6]
set_disable_timing sb_1__1_/chanx_left_out[6] set_disable_timing sb_1__1_/chanx_left_out[6]
set_disable_timing sb_1__1_/chanx_left_in[7] set_disable_timing sb_1__1_/chanx_left_in[7]
set_disable_timing sb_1__1_/chanx_left_out[7] set_disable_timing sb_1__1_/chanx_left_out[7]
set_disable_timing sb_1__1_/chanx_left_in[8]
set_disable_timing sb_1__1_/chanx_left_out[8] set_disable_timing sb_1__1_/chanx_left_out[8]
set_disable_timing sb_1__1_/chanx_left_in[9] set_disable_timing sb_1__1_/chanx_left_in[9]
set_disable_timing sb_1__1_/chanx_left_out[9] set_disable_timing sb_1__1_/chanx_left_out[9]
@ -1124,7 +1101,6 @@ set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__p
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0]
set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0]
set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0]
@ -1185,7 +1161,6 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3]
set_disable_timing sb_1__1_/mux_left_track_15/in[2] set_disable_timing sb_1__1_/mux_left_track_15/in[2]
set_disable_timing sb_1__1_/mux_left_track_17/in[2] set_disable_timing sb_1__1_/mux_left_track_17/in[2]
set_disable_timing sb_1__1_/mux_left_track_5/in[0] set_disable_timing sb_1__1_/mux_left_track_5/in[0]
set_disable_timing sb_1__1_/mux_left_track_7/in[0]
set_disable_timing sb_1__1_/mux_left_track_9/in[0] set_disable_timing sb_1__1_/mux_left_track_9/in[0]
set_disable_timing sb_1__1_/mux_left_track_11/in[0] set_disable_timing sb_1__1_/mux_left_track_11/in[0]
set_disable_timing sb_1__1_/mux_left_track_13/in[0] set_disable_timing sb_1__1_/mux_left_track_13/in[0]
@ -1218,12 +1193,12 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1]
####################################### #######################################
# Disable unused pins for pb_graph_node clb[0] # Disable unused pins for pb_graph_node clb[0]
####################################### #######################################
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[1]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0]
@ -1234,8 +1209,8 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0]
# Disable unused mux_inputs for pb_graph_node clb[0] # Disable unused mux_inputs for pb_graph_node clb[0]
####################################### #######################################
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5]
set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6]
@ -1564,31 +1539,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/*
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
####################################### #######################################
# Disable Timing for unused resources in grid[2][1][3] # Disable Timing for unused grid[2][1][3]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_inpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_0_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
#######################################
# Disable Timing for unused grid[2][1][4]
####################################### #######################################
####################################### #######################################
# Disable all the ports for pb_graph_node io[0] # Disable all the ports for pb_graph_node io[0]
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/*
####################################### #######################################
# Disable all the ports for pb_graph_node iopad[0] # Disable all the ports for pb_graph_node iopad[0]
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused resources in grid[2][1][4]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0]
####################################### #######################################
# Disable Timing for unused grid[2][1][5] # Disable Timing for unused grid[2][1][5]
####################################### #######################################
@ -1612,16 +1587,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/*
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/*
####################################### #######################################
# Disable Timing for unused grid[2][1][7] # Disable Timing for unused resources in grid[2][1][7]
####################################### #######################################
####################################### #######################################
# Disable all the ports for pb_graph_node io[0] # Disable unused pins for pb_graph_node io[0]
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/io_outpad[0]
####################################### #######################################
# Disable all the ports for pb_graph_node iopad[0] # Disable unused mux_inputs for pb_graph_node io[0]
####################################### #######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
####################################### #######################################
# Disable Timing for grid[1][0] # Disable Timing for grid[1][0]
####################################### #######################################
@ -1728,46 +1707,42 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/*
####################################### #######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/*
####################################### #######################################
# Disable Timing for unused resources in grid[0][1][1] # Disable Timing for unused grid[0][1][1]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/io_outpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused resources in grid[0][1][2]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/io_outpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
#######################################
# Disable Timing for unused grid[0][1][3]
####################################### #######################################
####################################### #######################################
# Disable all the ports for pb_graph_node io[0] # Disable all the ports for pb_graph_node io[0]
####################################### #######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/* set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/*
####################################### #######################################
# Disable all the ports for pb_graph_node iopad[0] # Disable all the ports for pb_graph_node iopad[0]
####################################### #######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused grid[0][1][2]
#######################################
#######################################
# Disable all the ports for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/*
#######################################
# Disable all the ports for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/*
#######################################
# Disable Timing for unused resources in grid[0][1][3]
#######################################
#######################################
# Disable unused pins for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/io_outpad[0]
#######################################
# Disable unused mux_inputs for pb_graph_node io[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0]
#######################################
# Disable unused pins for pb_graph_node iopad[0]
#######################################
set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0]
####################################### #######################################
# Disable Timing for unused grid[0][1][4] # Disable Timing for unused grid[0][1][4]
####################################### #######################################

94
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v
View File

@ -42,14 +42,14 @@ wire [0:0] clk_fm;
// ----- End Connect Global ports of FPGA top module ----- // ----- End Connect Global ports of FPGA top module -----
// ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- // ----- Link BLIF Benchmark I/Os to FPGA I/Os -----
// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] ----- // ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[27] -----
assign gfpga_pad_GPIO_PAD_fm[26] = a[0]; assign gfpga_pad_GPIO_PAD_fm[27] = a[0];
// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[25] ----- // ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[15] -----
assign gfpga_pad_GPIO_PAD_fm[25] = b[0]; assign gfpga_pad_GPIO_PAD_fm[15] = b[0];
// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] ----- // ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] -----
assign c[0] = gfpga_pad_GPIO_PAD_fm[11]; assign c[0] = gfpga_pad_GPIO_PAD_fm[12];
// ----- Wire unused FPGA I/Os to constants ----- // ----- Wire unused FPGA I/Os to constants -----
assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0;
@ -63,10 +63,9 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0;
@ -76,7 +75,8 @@ wire [0:0] clk_fm;
assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0;
assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0;
@ -125,14 +125,14 @@ initial begin
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}};
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111;
force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@ -155,10 +155,10 @@ initial begin
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
@ -197,14 +197,14 @@ initial begin
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1;
force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0;
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = 3'b011; force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = 3'b100; force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = 2'b01; force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = 2'b10; force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
@ -241,8 +241,8 @@ initial begin
force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}};
@ -265,8 +265,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}};
@ -291,8 +291,8 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}};
@ -303,14 +303,14 @@ initial begin
force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = 3'b001;
force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = 3'b110;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10;
force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01;
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}};
@ -385,8 +385,8 @@ initial begin
force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}};
force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}};
force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}};
@ -443,16 +443,16 @@ initial begin
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = 3'b110;
force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = 3'b001;
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}}; force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = 3'b101; force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = 3'b010; force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
@ -475,18 +475,18 @@ initial begin
force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101;
force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010;
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}};
force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}};

284
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit
View File

@ -3,7 +3,7 @@
// Bitstream width (LSB -> MSB): 1 // Bitstream width (LSB -> MSB): 1
1 1
1 1
0 1
0 0
0 0
0 0
@ -14,9 +14,9 @@
0 0
0 0
1 1
0 1
0 1
0 1
0 0
0 0
0 0
@ -143,12 +143,9 @@
0 0
0 0
0 0
0 1
0 1
0 1
0
0
0
0 0
0 0
0 0
@ -159,9 +156,8 @@
0 0
0 0
1 1
1
1
0 0
1
0 0
0 0
0 0
@ -261,6 +257,9 @@
0 0
1 1
1 1
0
0
1
1 1
1 1
1 1
@ -270,39 +269,6 @@
1 1
1 1
1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1 1
0 0
0 0
@ -336,32 +302,10 @@
0 0
0 0
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1 1
1 1
0 0
0 0
0
0
0
1 1
1 1
0 0
@ -405,80 +349,136 @@
0 0
0 0
0 0
0 1
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 1
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0 1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1 1
1 1
0 0
@ -515,7 +515,6 @@
1 1
1 1
1 1
1
0 0
1 1
1 1
@ -528,3 +527,4 @@
1 1
1 1
1 1
1

70
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml
View File

@ -10,7 +10,7 @@
</bit> </bit>
<bit id="525" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]"> <bit id="525" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[2]">
</bit> </bit>
<bit id="524" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]"> <bit id="524" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[1]">
</bit> </bit>
<bit id="523" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]"> <bit id="523" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0]">
</bit> </bit>
@ -32,11 +32,11 @@
</bit> </bit>
<bit id="514" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]"> <bit id="514" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[3]">
</bit> </bit>
<bit id="513" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]"> <bit id="513" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[2]">
</bit> </bit>
<bit id="512" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]"> <bit id="512" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[1]">
</bit> </bit>
<bit id="511" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]"> <bit id="511" value="1" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0]">
</bit> </bit>
<bit id="510" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]"> <bit id="510" value="0" path="fpga_top.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[3]">
</bit> </bit>
@ -290,11 +290,11 @@
</bit> </bit>
<bit id="385" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_1.mem_out[0]"> <bit id="385" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_1.mem_out[0]">
</bit> </bit>
<bit id="384" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[2]"> <bit id="384" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[2]">
</bit> </bit>
<bit id="383" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[1]"> <bit id="383" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[1]">
</bit> </bit>
<bit id="382" value="0" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[0]"> <bit id="382" value="1" path="fpga_top.cby_1__1_.mem_right_ipin_0.mem_out[0]">
</bit> </bit>
<bit id="381" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_7.mem_out[2]"> <bit id="381" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_7.mem_out[2]">
</bit> </bit>
@ -314,17 +314,17 @@
</bit> </bit>
<bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]"> <bit id="373" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_5.mem_out[0]">
</bit> </bit>
<bit id="372" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]"> <bit id="372" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[2]">
</bit> </bit>
<bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]"> <bit id="371" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[1]">
</bit> </bit>
<bit id="370" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]"> <bit id="370" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_4.mem_out[0]">
</bit> </bit>
<bit id="369" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]"> <bit id="369" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[2]">
</bit> </bit>
<bit id="368" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[1]"> <bit id="368" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[1]">
</bit> </bit>
<bit id="367" value="1" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[0]"> <bit id="367" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_3.mem_out[0]">
</bit> </bit>
<bit id="366" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_2.mem_out[2]"> <bit id="366" value="0" path="fpga_top.cby_1__1_.mem_left_ipin_2.mem_out[2]">
</bit> </bit>
@ -506,7 +506,7 @@
</bit> </bit>
<bit id="277" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]"> <bit id="277" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[1]">
</bit> </bit>
<bit id="276" value="0" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]"> <bit id="276" value="1" path="fpga_top.sb_1__0_.mem_top_track_8.mem_out[0]">
</bit> </bit>
<bit id="275" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]"> <bit id="275" value="0" path="fpga_top.sb_1__0_.mem_top_track_6.mem_out[1]">
</bit> </bit>
@ -516,7 +516,7 @@
</bit> </bit>
<bit id="272" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]"> <bit id="272" value="1" path="fpga_top.sb_1__0_.mem_top_track_4.mem_out[0]">
</bit> </bit>
<bit id="271" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]"> <bit id="271" value="1" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[2]">
</bit> </bit>
<bit id="270" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[1]"> <bit id="270" value="0" path="fpga_top.sb_1__0_.mem_top_track_2.mem_out[1]">
</bit> </bit>
@ -592,17 +592,17 @@
</bit> </bit>
<bit id="234" value="0" path="fpga_top.cby_0__1_.mem_right_ipin_0.mem_out[0]"> <bit id="234" value="0" path="fpga_top.cby_0__1_.mem_right_ipin_0.mem_out[0]">
</bit> </bit>
<bit id="233" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[2]"> <bit id="233" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[2]">
</bit> </bit>
<bit id="232" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[1]"> <bit id="232" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[1]">
</bit> </bit>
<bit id="231" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[0]"> <bit id="231" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_1.mem_out[0]">
</bit> </bit>
<bit id="230" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[2]"> <bit id="230" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[2]">
</bit> </bit>
<bit id="229" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[1]"> <bit id="229" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[1]">
</bit> </bit>
<bit id="228" value="1" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[0]"> <bit id="228" value="0" path="fpga_top.cby_0__1_.mem_left_ipin_0.mem_out[0]">
</bit> </bit>
<bit id="227" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[1]"> <bit id="227" value="0" path="fpga_top.sb_0__0_.mem_right_track_24.mem_out[1]">
</bit> </bit>
@ -616,9 +616,9 @@
</bit> </bit>
<bit id="222" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]"> <bit id="222" value="0" path="fpga_top.sb_0__0_.mem_right_track_20.mem_out[0]">
</bit> </bit>
<bit id="221" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]"> <bit id="221" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[1]">
</bit> </bit>
<bit id="220" value="0" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]"> <bit id="220" value="1" path="fpga_top.sb_0__0_.mem_right_track_18.mem_out[0]">
</bit> </bit>
<bit id="219" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]"> <bit id="219" value="0" path="fpga_top.sb_0__0_.mem_right_track_16.mem_out[1]">
</bit> </bit>
@ -702,21 +702,21 @@
</bit> </bit>
<bit id="179" value="0" path="fpga_top.sb_0__0_.mem_top_track_8.mem_out[0]"> <bit id="179" value="0" path="fpga_top.sb_0__0_.mem_top_track_8.mem_out[0]">
</bit> </bit>
<bit id="178" value="0" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[1]"> <bit id="178" value="1" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[1]">
</bit> </bit>
<bit id="177" value="0" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[0]"> <bit id="177" value="1" path="fpga_top.sb_0__0_.mem_top_track_6.mem_out[0]">
</bit> </bit>
<bit id="176" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[1]"> <bit id="176" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[1]">
</bit> </bit>
<bit id="175" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[0]"> <bit id="175" value="0" path="fpga_top.sb_0__0_.mem_top_track_4.mem_out[0]">
</bit> </bit>
<bit id="174" value="1" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[1]"> <bit id="174" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[1]">
</bit> </bit>
<bit id="173" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[0]"> <bit id="173" value="0" path="fpga_top.sb_0__0_.mem_top_track_2.mem_out[0]">
</bit> </bit>
<bit id="172" value="1" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]"> <bit id="172" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[2]">
</bit> </bit>
<bit id="171" value="1" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[1]"> <bit id="171" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[1]">
</bit> </bit>
<bit id="170" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[0]"> <bit id="170" value="0" path="fpga_top.sb_0__0_.mem_top_track_0.mem_out[0]">
</bit> </bit>
@ -736,9 +736,9 @@
</bit> </bit>
<bit id="162" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]"> <bit id="162" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_19.mem_out[0]">
</bit> </bit>
<bit id="161" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]"> <bit id="161" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[1]">
</bit> </bit>
<bit id="160" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]"> <bit id="160" value="1" path="fpga_top.sb_0__1_.mem_bottom_track_17.mem_out[0]">
</bit> </bit>
<bit id="159" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]"> <bit id="159" value="0" path="fpga_top.sb_0__1_.mem_bottom_track_15.mem_out[2]">
</bit> </bit>
@ -796,7 +796,7 @@
</bit> </bit>
<bit id="132" value="0" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[1]"> <bit id="132" value="0" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[1]">
</bit> </bit>
<bit id="131" value="0" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[0]"> <bit id="131" value="1" path="fpga_top.sb_0__1_.mem_right_track_16.mem_out[0]">
</bit> </bit>
<bit id="130" value="0" path="fpga_top.sb_0__1_.mem_right_track_14.mem_out[1]"> <bit id="130" value="0" path="fpga_top.sb_0__1_.mem_right_track_14.mem_out[1]">
</bit> </bit>
@ -864,9 +864,9 @@
</bit> </bit>
<bit id="98" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[2]"> <bit id="98" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[2]">
</bit> </bit>
<bit id="97" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]"> <bit id="97" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[1]">
</bit> </bit>
<bit id="96" value="0" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]"> <bit id="96" value="1" path="fpga_top.cbx_1__1_.mem_top_ipin_0.mem_out[0]">
</bit> </bit>
<bit id="95" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_7.mem_out[2]"> <bit id="95" value="0" path="fpga_top.cbx_1__1_.mem_bottom_ipin_7.mem_out[2]">
</bit> </bit>
@ -954,9 +954,9 @@
</bit> </bit>
<bit id="53" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]"> <bit id="53" value="0" path="fpga_top.sb_1__1_.mem_left_track_9.mem_out[0]">
</bit> </bit>
<bit id="52" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]"> <bit id="52" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[1]">
</bit> </bit>
<bit id="51" value="0" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]"> <bit id="51" value="1" path="fpga_top.sb_1__1_.mem_left_track_7.mem_out[0]">
</bit> </bit>
<bit id="50" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]"> <bit id="50" value="0" path="fpga_top.sb_1__1_.mem_left_track_5.mem_out[1]">
</bit> </bit>
@ -1034,9 +1034,9 @@
</bit> </bit>
<bit id="13" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]"> <bit id="13" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit> </bit>
<bit id="12" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]"> <bit id="12" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit> </bit>
<bit id="11" value="0" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]"> <bit id="11" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit> </bit>
<bit id="10" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]"> <bit id="10" value="1" path="fpga_top.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0]">
</bit> </bit>

266
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml
View File

@ -431,14 +431,14 @@
<instance level="3" name="mem_fle_3_in_0"/> <instance level="3" name="mem_fle_3_in_0"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="b"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
<path id="6" net_name="unmapped"/> <path id="6" net_name="unmapped"/>
<path id="7" net_name="a"/> <path id="7" net_name="unmapped"/>
<path id="8" net_name="unmapped"/> <path id="8" net_name="unmapped"/>
<path id="9" net_name="unmapped"/> <path id="9" net_name="unmapped"/>
<path id="10" net_name="unmapped"/> <path id="10" net_name="unmapped"/>
@ -449,10 +449,10 @@
<output_nets> <output_nets>
<path id="0" net_name="a"/> <path id="0" net_name="a"/>
</output_nets> </output_nets>
<bitstream path_id="7"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/> <bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[3]" value="1"/> <bit memory_port="mem_out[3]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
@ -498,14 +498,14 @@
<instance level="3" name="mem_fle_3_in_3"/> <instance level="3" name="mem_fle_3_in_3"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="b"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
<path id="6" net_name="unmapped"/> <path id="6" net_name="unmapped"/>
<path id="7" net_name="a"/> <path id="7" net_name="unmapped"/>
<path id="8" net_name="unmapped"/> <path id="8" net_name="unmapped"/>
<path id="9" net_name="unmapped"/> <path id="9" net_name="unmapped"/>
<path id="10" net_name="unmapped"/> <path id="10" net_name="unmapped"/>
@ -516,9 +516,9 @@
<output_nets> <output_nets>
<path id="0" net_name="b"/> <path id="0" net_name="b"/>
</output_nets> </output_nets>
<bitstream path_id="3"> <bitstream path_id="1">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="1"/>
<bit memory_port="mem_out[3]" value="1"/> <bit memory_port="mem_out[3]" value="1"/>
</bitstream> </bitstream>
@ -715,7 +715,7 @@
<instance level="4" name="GPIO_DFF_mem"/> <instance level="4" name="GPIO_DFF_mem"/>
</hierarchy> </hierarchy>
<bitstream> <bitstream>
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
</bitstream_block> </bitstream_block>
@ -731,7 +731,7 @@
<instance level="4" name="GPIO_DFF_mem"/> <instance level="4" name="GPIO_DFF_mem"/>
</hierarchy> </hierarchy>
<bitstream> <bitstream>
<bit memory_port="mem_out[0]" value="1"/> <bit memory_port="mem_out[0]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
</bitstream_block> </bitstream_block>
@ -1054,17 +1054,17 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
</output_nets> </output_nets>
<bitstream path_id="1"> <bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_top_track_2" hierarchy_level="2"> <bitstream_block name="mem_top_track_2" hierarchy_level="2">
@ -1074,16 +1074,16 @@
<instance level="2" name="mem_top_track_2"/> <instance level="2" name="mem_top_track_2"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
</output_nets> </output_nets>
<bitstream path_id="1"> <bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/> <bit memory_port="mem_out[1]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_top_track_4" hierarchy_level="2"> <bitstream_block name="mem_top_track_4" hierarchy_level="2">
@ -1093,8 +1093,8 @@
<instance level="2" name="mem_top_track_4"/> <instance level="2" name="mem_top_track_4"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="a"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -1112,16 +1112,16 @@
<instance level="2" name="mem_top_track_6"/> <instance level="2" name="mem_top_track_6"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_top_track_8" hierarchy_level="2"> <bitstream_block name="mem_top_track_8" hierarchy_level="2">
@ -1190,7 +1190,7 @@
<instance level="2" name="mem_top_track_14"/> <instance level="2" name="mem_top_track_14"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
@ -1209,7 +1209,7 @@
<instance level="2" name="mem_top_track_16"/> <instance level="2" name="mem_top_track_16"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
@ -1228,7 +1228,7 @@
<instance level="2" name="mem_top_track_18"/> <instance level="2" name="mem_top_track_18"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -1480,15 +1480,15 @@
<instance level="2" name="mem_right_track_18"/> <instance level="2" name="mem_right_track_18"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_right_track_20" hierarchy_level="2"> <bitstream_block name="mem_right_track_20" hierarchy_level="2">
@ -1713,13 +1713,13 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="a"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="2">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
@ -1749,7 +1749,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/> <path id="1" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -1767,7 +1767,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/> <path id="1" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -1826,7 +1826,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="b"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -1846,8 +1846,8 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="b"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -1865,8 +1865,8 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="a"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -1884,7 +1884,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="a"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -1961,16 +1961,16 @@
<instance level="2" name="mem_bottom_track_17"/> <instance level="2" name="mem_bottom_track_17"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
<path id="1" net_name="b"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_bottom_track_19" hierarchy_level="2"> <bitstream_block name="mem_bottom_track_19" hierarchy_level="2">
@ -1981,7 +1981,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="a"/> <path id="1" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -1999,7 +1999,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="c"/> <path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="a"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="c"/> <path id="0" net_name="c"/>
@ -2077,16 +2077,16 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="b"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="2">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="0"/> <bit memory_port="mem_out[2]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_top_track_4" hierarchy_level="2"> <bitstream_block name="mem_top_track_4" hierarchy_level="2">
@ -2136,13 +2136,13 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="c"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="2">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
@ -2193,7 +2193,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -2213,7 +2213,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -2559,7 +2559,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -2675,7 +2675,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -2695,8 +2695,8 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="b"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="a"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -2845,7 +2845,7 @@
<instance level="2" name="mem_left_track_5"/> <instance level="2" name="mem_left_track_5"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="b"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
@ -2869,11 +2869,11 @@
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_left_track_9" hierarchy_level="2"> <bitstream_block name="mem_left_track_9" hierarchy_level="2">
@ -2902,7 +2902,7 @@
<instance level="2" name="mem_left_track_11"/> <instance level="2" name="mem_left_track_11"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
</input_nets> </input_nets>
@ -3128,7 +3128,7 @@
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="c"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -3266,7 +3266,7 @@
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="c"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -3287,7 +3287,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="c"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
@ -3360,7 +3360,7 @@
<path id="1" net_name="c"/> <path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="a"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
@ -3382,7 +3382,7 @@
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="c"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
@ -3403,7 +3403,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
@ -3498,15 +3498,15 @@
<path id="1" net_name="c"/> <path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="a"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="4">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/> <bit memory_port="mem_out[2]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
@ -3519,7 +3519,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="a"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
@ -3541,7 +3541,7 @@
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="c"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
@ -3565,7 +3565,7 @@
<instance level="2" name="mem_left_ipin_0"/> <instance level="2" name="mem_left_ipin_0"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3573,12 +3573,12 @@
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
</output_nets> </output_nets>
<bitstream path_id="0"> <bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="1"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_left_ipin_1" hierarchy_level="2"> <bitstream_block name="mem_left_ipin_1" hierarchy_level="2">
@ -3588,20 +3588,20 @@
<instance level="2" name="mem_left_ipin_1"/> <instance level="2" name="mem_left_ipin_1"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="a"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
</output_nets> </output_nets>
<bitstream path_id="2"> <bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="1"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_right_ipin_0" hierarchy_level="2"> <bitstream_block name="mem_right_ipin_0" hierarchy_level="2">
@ -3611,12 +3611,12 @@
<instance level="2" name="mem_right_ipin_0"/> <instance level="2" name="mem_right_ipin_0"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="c"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -3636,7 +3636,7 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="a"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
@ -3657,7 +3657,7 @@
<instance level="2" name="mem_right_ipin_2"/> <instance level="2" name="mem_right_ipin_2"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="a"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3726,7 +3726,7 @@
<instance level="2" name="mem_right_ipin_5"/> <instance level="2" name="mem_right_ipin_5"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="b"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3749,12 +3749,12 @@
<instance level="2" name="mem_right_ipin_6"/> <instance level="2" name="mem_right_ipin_6"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="a"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="c"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
@ -3775,7 +3775,7 @@
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="c"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
@ -3822,7 +3822,7 @@
<input_nets> <input_nets>
<path id="0" net_name="c"/> <path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="b"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
@ -3843,7 +3843,7 @@
<instance level="2" name="mem_left_ipin_2"/> <instance level="2" name="mem_left_ipin_2"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="b"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="c"/> <path id="2" net_name="c"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3874,12 +3874,12 @@
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="c"/> <path id="0" net_name="unmapped"/>
</output_nets> </output_nets>
<bitstream path_id="0"> <bitstream path_id="-1">
<bit memory_port="mem_out[0]" value="1"/> <bit memory_port="mem_out[0]" value="0"/>
<bit memory_port="mem_out[1]" value="1"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="1"/> <bit memory_port="mem_out[2]" value="0"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_left_ipin_4" hierarchy_level="2"> <bitstream_block name="mem_left_ipin_4" hierarchy_level="2">
@ -3891,18 +3891,18 @@
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="unmapped"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="c"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
<path id="4" net_name="unmapped"/> <path id="4" net_name="unmapped"/>
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="2">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="0"/>
<bit memory_port="mem_out[2]" value="0"/> <bit memory_port="mem_out[2]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_left_ipin_5" hierarchy_level="2"> <bitstream_block name="mem_left_ipin_5" hierarchy_level="2">
@ -3912,7 +3912,7 @@
<instance level="2" name="mem_left_ipin_5"/> <instance level="2" name="mem_left_ipin_5"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="c"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3981,7 +3981,7 @@
<instance level="2" name="mem_right_ipin_0"/> <instance level="2" name="mem_right_ipin_0"/>
</hierarchy> </hierarchy>
<input_nets> <input_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="b"/>
<path id="1" net_name="unmapped"/> <path id="1" net_name="unmapped"/>
<path id="2" net_name="unmapped"/> <path id="2" net_name="unmapped"/>
<path id="3" net_name="unmapped"/> <path id="3" net_name="unmapped"/>
@ -3989,12 +3989,12 @@
<path id="5" net_name="unmapped"/> <path id="5" net_name="unmapped"/>
</input_nets> </input_nets>
<output_nets> <output_nets>
<path id="0" net_name="unmapped"/> <path id="0" net_name="b"/>
</output_nets> </output_nets>
<bitstream path_id="-1"> <bitstream path_id="0">
<bit memory_port="mem_out[0]" value="0"/> <bit memory_port="mem_out[0]" value="1"/>
<bit memory_port="mem_out[1]" value="0"/> <bit memory_port="mem_out[1]" value="1"/>
<bit memory_port="mem_out[2]" value="0"/> <bit memory_port="mem_out[2]" value="1"/>
</bitstream> </bitstream>
</bitstream_block> </bitstream_block>
<bitstream_block name="mem_right_ipin_1" hierarchy_level="2"> <bitstream_block name="mem_right_ipin_1" hierarchy_level="2">

2
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc
View File

@ -14,7 +14,7 @@ set_units -time s
################################################## ##################################################
# Create clock # Create clock
################################################## ##################################################
create_clock -name clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} [get_ports {clk[0]}] create_clock -name clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} [get_ports {clk[0]}]
################################################## ##################################################
# Create programmable clock # Create programmable clock
################################################## ##################################################

6
openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml
View File

@ -3,7 +3,7 @@
--> -->
<io_mapping> <io_mapping>
<io name="gfpga_pad_GPIO_PAD[26:26]" net="a" dir="input"/> <io name="gfpga_pad_GPIO_PAD[27:27]" net="a" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[25:25]" net="b" dir="input"/> <io name="gfpga_pad_GPIO_PAD[15:15]" net="b" dir="input"/>
<io name="gfpga_pad_GPIO_PAD[11:11]" net="c" dir="output"/> <io name="gfpga_pad_GPIO_PAD[12:12]" net="c" dir="output"/>
</io_mapping> </io_mapping>