diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v index b02d4881b..f82c458e3 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v @@ -50,7 +50,7 @@ module and2_top_formal_verification_random_tb; initial begin clk[0] <= 1'b0; while(1) begin - #0.5744515657 + #0.7626540661 clk[0] <= !clk[0]; end end @@ -109,7 +109,7 @@ initial begin $timeformat(-9, 2, "ns", 20); $display("Simulation start"); // ----- Can be changed by the user for his/her need ------- - #8.042322159 + #10.6771574 if(nb_error == 0) begin $display("Simulation Succeed"); end else begin diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc index 4310fdd1e..acf0f91b8 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_fpga_top_analysis.sdc @@ -9,14 +9,14 @@ ################################################## # Create clock ################################################## -create_clock clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} +create_clock clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} ################################################## # Create input and output delays for used I/Os ################################################## -set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[26] -set_input_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[25] -set_output_delay -clock clk[0] -max 1.148903084e-09 gfpga_pad_GPIO_PAD[11] +set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[27] +set_input_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[15] +set_output_delay -clock clk[0] -max 1.525308102e-09 gfpga_pad_GPIO_PAD[12] ################################################## # Disable timing for unused I/Os @@ -32,10 +32,9 @@ set_disable_timing gfpga_pad_GPIO_PAD[7] set_disable_timing gfpga_pad_GPIO_PAD[8] set_disable_timing gfpga_pad_GPIO_PAD[9] set_disable_timing gfpga_pad_GPIO_PAD[10] -set_disable_timing gfpga_pad_GPIO_PAD[12] +set_disable_timing gfpga_pad_GPIO_PAD[11] set_disable_timing gfpga_pad_GPIO_PAD[13] set_disable_timing gfpga_pad_GPIO_PAD[14] -set_disable_timing gfpga_pad_GPIO_PAD[15] set_disable_timing gfpga_pad_GPIO_PAD[16] set_disable_timing gfpga_pad_GPIO_PAD[17] set_disable_timing gfpga_pad_GPIO_PAD[18] @@ -45,7 +44,8 @@ set_disable_timing gfpga_pad_GPIO_PAD[21] set_disable_timing gfpga_pad_GPIO_PAD[22] set_disable_timing gfpga_pad_GPIO_PAD[23] set_disable_timing gfpga_pad_GPIO_PAD[24] -set_disable_timing gfpga_pad_GPIO_PAD[27] +set_disable_timing gfpga_pad_GPIO_PAD[25] +set_disable_timing gfpga_pad_GPIO_PAD[26] set_disable_timing gfpga_pad_GPIO_PAD[28] set_disable_timing gfpga_pad_GPIO_PAD[29] set_disable_timing gfpga_pad_GPIO_PAD[30] @@ -156,7 +156,6 @@ set_disable_timing cbx_1__0_/chanx_left_in[7] set_disable_timing cbx_1__0_/chanx_right_in[7] set_disable_timing cbx_1__0_/chanx_left_in[8] set_disable_timing cbx_1__0_/chanx_right_in[8] -set_disable_timing cbx_1__0_/chanx_left_in[9] set_disable_timing cbx_1__0_/chanx_right_in[9] set_disable_timing cbx_1__0_/chanx_left_in[10] set_disable_timing cbx_1__0_/chanx_right_in[10] @@ -181,7 +180,6 @@ set_disable_timing cbx_1__0_/chanx_left_out[7] set_disable_timing cbx_1__0_/chanx_right_out[7] set_disable_timing cbx_1__0_/chanx_left_out[8] set_disable_timing cbx_1__0_/chanx_right_out[8] -set_disable_timing cbx_1__0_/chanx_left_out[9] set_disable_timing cbx_1__0_/chanx_right_out[9] set_disable_timing cbx_1__0_/chanx_left_out[10] set_disable_timing cbx_1__0_/chanx_right_out[10] @@ -274,7 +272,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[1] set_disable_timing cbx_1__1_/chanx_left_in[2] set_disable_timing cbx_1__1_/chanx_right_in[2] set_disable_timing cbx_1__1_/chanx_left_in[3] -set_disable_timing cbx_1__1_/chanx_right_in[3] set_disable_timing cbx_1__1_/chanx_left_in[4] set_disable_timing cbx_1__1_/chanx_right_in[4] set_disable_timing cbx_1__1_/chanx_left_in[5] @@ -283,7 +280,6 @@ set_disable_timing cbx_1__1_/chanx_left_in[6] set_disable_timing cbx_1__1_/chanx_right_in[6] set_disable_timing cbx_1__1_/chanx_left_in[7] set_disable_timing cbx_1__1_/chanx_right_in[7] -set_disable_timing cbx_1__1_/chanx_left_in[8] set_disable_timing cbx_1__1_/chanx_right_in[8] set_disable_timing cbx_1__1_/chanx_left_in[9] set_disable_timing cbx_1__1_/chanx_right_in[9] @@ -299,7 +295,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[1] set_disable_timing cbx_1__1_/chanx_left_out[2] set_disable_timing cbx_1__1_/chanx_right_out[2] set_disable_timing cbx_1__1_/chanx_left_out[3] -set_disable_timing cbx_1__1_/chanx_right_out[3] set_disable_timing cbx_1__1_/chanx_left_out[4] set_disable_timing cbx_1__1_/chanx_right_out[4] set_disable_timing cbx_1__1_/chanx_left_out[5] @@ -308,7 +303,6 @@ set_disable_timing cbx_1__1_/chanx_left_out[6] set_disable_timing cbx_1__1_/chanx_right_out[6] set_disable_timing cbx_1__1_/chanx_left_out[7] set_disable_timing cbx_1__1_/chanx_right_out[7] -set_disable_timing cbx_1__1_/chanx_left_out[8] set_disable_timing cbx_1__1_/chanx_right_out[8] set_disable_timing cbx_1__1_/chanx_left_out[9] set_disable_timing cbx_1__1_/chanx_right_out[9] @@ -326,7 +320,6 @@ set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_4__pin_out set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] -set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] set_disable_timing cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] set_disable_timing cbx_1__1_/mux_bottom_ipin_0/in[1] @@ -374,7 +367,6 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_1/in[4] set_disable_timing cbx_1__1_/mux_bottom_ipin_7/in[4] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[2] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[5] -set_disable_timing cbx_1__1_/mux_top_ipin_0/in[5] set_disable_timing cbx_1__1_/mux_top_ipin_1/in[3] set_disable_timing cbx_1__1_/mux_bottom_ipin_2/in[4] set_disable_timing cbx_1__1_/mux_top_ipin_0/in[4] @@ -398,11 +390,12 @@ set_disable_timing cbx_1__1_/mux_bottom_ipin_6/in[4] ################################################## # Disable timing for Connection block cby_0__1_ ################################################## +set_disable_timing cby_0__1_/chany_bottom_in[0] set_disable_timing cby_0__1_/chany_top_in[0] +set_disable_timing cby_0__1_/chany_bottom_in[1] set_disable_timing cby_0__1_/chany_top_in[1] set_disable_timing cby_0__1_/chany_bottom_in[2] set_disable_timing cby_0__1_/chany_top_in[2] -set_disable_timing cby_0__1_/chany_bottom_in[3] set_disable_timing cby_0__1_/chany_top_in[3] set_disable_timing cby_0__1_/chany_bottom_in[4] set_disable_timing cby_0__1_/chany_top_in[4] @@ -413,7 +406,6 @@ set_disable_timing cby_0__1_/chany_top_in[6] set_disable_timing cby_0__1_/chany_bottom_in[7] set_disable_timing cby_0__1_/chany_top_in[7] set_disable_timing cby_0__1_/chany_bottom_in[8] -set_disable_timing cby_0__1_/chany_top_in[8] set_disable_timing cby_0__1_/chany_bottom_in[9] set_disable_timing cby_0__1_/chany_top_in[9] set_disable_timing cby_0__1_/chany_bottom_in[10] @@ -421,11 +413,12 @@ set_disable_timing cby_0__1_/chany_bottom_in[11] set_disable_timing cby_0__1_/chany_top_in[11] set_disable_timing cby_0__1_/chany_bottom_in[12] set_disable_timing cby_0__1_/chany_top_in[12] +set_disable_timing cby_0__1_/chany_bottom_out[0] set_disable_timing cby_0__1_/chany_top_out[0] +set_disable_timing cby_0__1_/chany_bottom_out[1] set_disable_timing cby_0__1_/chany_top_out[1] set_disable_timing cby_0__1_/chany_bottom_out[2] set_disable_timing cby_0__1_/chany_top_out[2] -set_disable_timing cby_0__1_/chany_bottom_out[3] set_disable_timing cby_0__1_/chany_top_out[3] set_disable_timing cby_0__1_/chany_bottom_out[4] set_disable_timing cby_0__1_/chany_top_out[4] @@ -436,7 +429,6 @@ set_disable_timing cby_0__1_/chany_top_out[6] set_disable_timing cby_0__1_/chany_bottom_out[7] set_disable_timing cby_0__1_/chany_top_out[7] set_disable_timing cby_0__1_/chany_bottom_out[8] -set_disable_timing cby_0__1_/chany_top_out[8] set_disable_timing cby_0__1_/chany_bottom_out[9] set_disable_timing cby_0__1_/chany_top_out[9] set_disable_timing cby_0__1_/chany_bottom_out[10] @@ -444,6 +436,8 @@ set_disable_timing cby_0__1_/chany_bottom_out[11] set_disable_timing cby_0__1_/chany_top_out[11] set_disable_timing cby_0__1_/chany_bottom_out[12] set_disable_timing cby_0__1_/chany_top_out[12] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] +set_disable_timing cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] @@ -452,11 +446,13 @@ set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_out set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] +set_disable_timing cby_0__1_/mux_left_ipin_0/in[1] set_disable_timing cby_0__1_/mux_left_ipin_1/in[1] set_disable_timing cby_0__1_/mux_right_ipin_5/in[1] set_disable_timing cby_0__1_/mux_left_ipin_0/in[0] set_disable_timing cby_0__1_/mux_left_ipin_1/in[0] set_disable_timing cby_0__1_/mux_right_ipin_5/in[0] +set_disable_timing cby_0__1_/mux_left_ipin_1/in[3] set_disable_timing cby_0__1_/mux_right_ipin_0/in[1] set_disable_timing cby_0__1_/mux_right_ipin_6/in[1] set_disable_timing cby_0__1_/mux_left_ipin_1/in[2] @@ -514,12 +510,10 @@ set_disable_timing cby_0__1_/mux_right_ipin_4/in[4] # Disable timing for Connection block cby_1__1_ ################################################## set_disable_timing cby_1__1_/chany_top_in[0] -set_disable_timing cby_1__1_/chany_bottom_in[1] set_disable_timing cby_1__1_/chany_top_in[1] set_disable_timing cby_1__1_/chany_top_in[2] set_disable_timing cby_1__1_/chany_bottom_in[3] set_disable_timing cby_1__1_/chany_top_in[3] -set_disable_timing cby_1__1_/chany_bottom_in[4] set_disable_timing cby_1__1_/chany_top_in[4] set_disable_timing cby_1__1_/chany_bottom_in[5] set_disable_timing cby_1__1_/chany_top_in[5] @@ -538,12 +532,10 @@ set_disable_timing cby_1__1_/chany_top_in[11] set_disable_timing cby_1__1_/chany_bottom_in[12] set_disable_timing cby_1__1_/chany_top_in[12] set_disable_timing cby_1__1_/chany_top_out[0] -set_disable_timing cby_1__1_/chany_bottom_out[1] set_disable_timing cby_1__1_/chany_top_out[1] set_disable_timing cby_1__1_/chany_top_out[2] set_disable_timing cby_1__1_/chany_bottom_out[3] set_disable_timing cby_1__1_/chany_top_out[3] -set_disable_timing cby_1__1_/chany_bottom_out[4] set_disable_timing cby_1__1_/chany_top_out[4] set_disable_timing cby_1__1_/chany_bottom_out[5] set_disable_timing cby_1__1_/chany_top_out[5] @@ -564,11 +556,10 @@ set_disable_timing cby_1__1_/chany_top_out[12] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_0__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_1__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_2__pin_outpad_0_[0] -set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_4__pin_outpad_0_[0] +set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_3__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_5__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_6__pin_outpad_0_[0] set_disable_timing cby_1__1_/right_grid_left_width_0_height_0_subtile_7__pin_outpad_0_[0] -set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_1_[0] set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_5_[0] set_disable_timing cby_1__1_/left_grid_right_width_0_height_0_subtile_0__pin_I_9_[0] set_disable_timing cby_1__1_/mux_left_ipin_0/in[1] @@ -579,11 +570,11 @@ set_disable_timing cby_1__1_/mux_left_ipin_1/in[0] set_disable_timing cby_1__1_/mux_left_ipin_7/in[0] set_disable_timing cby_1__1_/mux_left_ipin_1/in[3] set_disable_timing cby_1__1_/mux_left_ipin_2/in[1] -set_disable_timing cby_1__1_/mux_right_ipin_0/in[1] set_disable_timing cby_1__1_/mux_left_ipin_1/in[2] set_disable_timing cby_1__1_/mux_left_ipin_2/in[0] set_disable_timing cby_1__1_/mux_right_ipin_0/in[0] set_disable_timing cby_1__1_/mux_left_ipin_2/in[3] +set_disable_timing cby_1__1_/mux_left_ipin_3/in[1] set_disable_timing cby_1__1_/mux_right_ipin_1/in[1] set_disable_timing cby_1__1_/mux_left_ipin_2/in[2] set_disable_timing cby_1__1_/mux_left_ipin_3/in[0] @@ -594,7 +585,6 @@ set_disable_timing cby_1__1_/mux_right_ipin_2/in[1] set_disable_timing cby_1__1_/mux_left_ipin_3/in[2] set_disable_timing cby_1__1_/mux_left_ipin_4/in[0] set_disable_timing cby_1__1_/mux_right_ipin_2/in[0] -set_disable_timing cby_1__1_/mux_left_ipin_4/in[3] set_disable_timing cby_1__1_/mux_left_ipin_5/in[1] set_disable_timing cby_1__1_/mux_left_ipin_4/in[2] set_disable_timing cby_1__1_/mux_left_ipin_5/in[0] @@ -639,11 +629,12 @@ set_disable_timing cby_1__1_/mux_left_ipin_6/in[4] ################################################## # Disable timing for Switch block sb_0__0_ ################################################## +set_disable_timing sb_0__0_/chany_top_out[0] set_disable_timing sb_0__0_/chany_top_in[0] +set_disable_timing sb_0__0_/chany_top_out[1] set_disable_timing sb_0__0_/chany_top_in[1] set_disable_timing sb_0__0_/chany_top_out[2] set_disable_timing sb_0__0_/chany_top_in[2] -set_disable_timing sb_0__0_/chany_top_out[3] set_disable_timing sb_0__0_/chany_top_in[3] set_disable_timing sb_0__0_/chany_top_out[4] set_disable_timing sb_0__0_/chany_top_in[4] @@ -654,7 +645,6 @@ set_disable_timing sb_0__0_/chany_top_in[6] set_disable_timing sb_0__0_/chany_top_out[7] set_disable_timing sb_0__0_/chany_top_in[7] set_disable_timing sb_0__0_/chany_top_out[8] -set_disable_timing sb_0__0_/chany_top_in[8] set_disable_timing sb_0__0_/chany_top_out[9] set_disable_timing sb_0__0_/chany_top_in[9] set_disable_timing sb_0__0_/chany_top_out[10] @@ -680,7 +670,6 @@ set_disable_timing sb_0__0_/chanx_right_out[7] set_disable_timing sb_0__0_/chanx_right_in[7] set_disable_timing sb_0__0_/chanx_right_out[8] set_disable_timing sb_0__0_/chanx_right_in[8] -set_disable_timing sb_0__0_/chanx_right_out[9] set_disable_timing sb_0__0_/chanx_right_in[9] set_disable_timing sb_0__0_/chanx_right_out[10] set_disable_timing sb_0__0_/chanx_right_in[10] @@ -688,7 +677,8 @@ set_disable_timing sb_0__0_/chanx_right_in[11] set_disable_timing sb_0__0_/chanx_right_out[12] set_disable_timing sb_0__0_/chanx_right_in[12] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_0__0_/top_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] @@ -706,12 +696,13 @@ set_disable_timing sb_0__0_/right_bottom_grid_top_width_0_height_0_subtile_7__pi set_disable_timing sb_0__0_/mux_top_track_0/in[0] set_disable_timing sb_0__0_/mux_top_track_12/in[0] set_disable_timing sb_0__0_/mux_top_track_24/in[0] +set_disable_timing sb_0__0_/mux_top_track_0/in[1] set_disable_timing sb_0__0_/mux_top_track_2/in[0] set_disable_timing sb_0__0_/mux_top_track_14/in[0] +set_disable_timing sb_0__0_/mux_top_track_2/in[1] set_disable_timing sb_0__0_/mux_top_track_4/in[0] set_disable_timing sb_0__0_/mux_top_track_16/in[0] set_disable_timing sb_0__0_/mux_top_track_4/in[1] -set_disable_timing sb_0__0_/mux_top_track_6/in[0] set_disable_timing sb_0__0_/mux_top_track_18/in[0] set_disable_timing sb_0__0_/mux_top_track_6/in[1] set_disable_timing sb_0__0_/mux_top_track_8/in[0] @@ -761,7 +752,6 @@ set_disable_timing sb_0__0_/mux_right_track_10/in[0] set_disable_timing sb_0__0_/mux_right_track_12/in[0] set_disable_timing sb_0__0_/mux_right_track_14/in[0] set_disable_timing sb_0__0_/mux_right_track_16/in[0] -set_disable_timing sb_0__0_/mux_right_track_18/in[0] set_disable_timing sb_0__0_/mux_right_track_20/in[0] set_disable_timing sb_0__0_/mux_right_track_24/in[0] set_disable_timing sb_0__0_/mux_right_track_0/in[0] @@ -787,7 +777,6 @@ set_disable_timing sb_0__1_/chanx_right_out[1] set_disable_timing sb_0__1_/chanx_right_out[2] set_disable_timing sb_0__1_/chanx_right_in[2] set_disable_timing sb_0__1_/chanx_right_out[3] -set_disable_timing sb_0__1_/chanx_right_in[3] set_disable_timing sb_0__1_/chanx_right_out[4] set_disable_timing sb_0__1_/chanx_right_in[4] set_disable_timing sb_0__1_/chanx_right_out[5] @@ -796,7 +785,6 @@ set_disable_timing sb_0__1_/chanx_right_out[6] set_disable_timing sb_0__1_/chanx_right_in[6] set_disable_timing sb_0__1_/chanx_right_out[7] set_disable_timing sb_0__1_/chanx_right_in[7] -set_disable_timing sb_0__1_/chanx_right_out[8] set_disable_timing sb_0__1_/chanx_right_in[8] set_disable_timing sb_0__1_/chanx_right_out[9] set_disable_timing sb_0__1_/chanx_right_in[9] @@ -806,11 +794,12 @@ set_disable_timing sb_0__1_/chanx_right_out[11] set_disable_timing sb_0__1_/chanx_right_in[11] set_disable_timing sb_0__1_/chanx_right_out[12] set_disable_timing sb_0__1_/chanx_right_in[12] +set_disable_timing sb_0__1_/chany_bottom_in[0] set_disable_timing sb_0__1_/chany_bottom_out[0] +set_disable_timing sb_0__1_/chany_bottom_in[1] set_disable_timing sb_0__1_/chany_bottom_out[1] set_disable_timing sb_0__1_/chany_bottom_in[2] set_disable_timing sb_0__1_/chany_bottom_out[2] -set_disable_timing sb_0__1_/chany_bottom_in[3] set_disable_timing sb_0__1_/chany_bottom_out[3] set_disable_timing sb_0__1_/chany_bottom_in[4] set_disable_timing sb_0__1_/chany_bottom_out[4] @@ -821,7 +810,6 @@ set_disable_timing sb_0__1_/chany_bottom_out[6] set_disable_timing sb_0__1_/chany_bottom_in[7] set_disable_timing sb_0__1_/chany_bottom_out[7] set_disable_timing sb_0__1_/chany_bottom_in[8] -set_disable_timing sb_0__1_/chany_bottom_out[8] set_disable_timing sb_0__1_/chany_bottom_in[9] set_disable_timing sb_0__1_/chany_bottom_out[9] set_disable_timing sb_0__1_/chany_bottom_in[10] @@ -840,7 +828,8 @@ set_disable_timing sb_0__1_/right_top_grid_bottom_width_0_height_0_subtile_7__pi set_disable_timing sb_0__1_/right_bottom_grid_top_width_0_height_0_subtile_0__pin_O_2_[0] set_disable_timing sb_0__1_/bottom_right_grid_left_width_0_height_0_subtile_0__pin_O_1_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_0__pin_inpad_0_[0] -set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_3__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_1__pin_inpad_0_[0] +set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_2__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_0__1_/bottom_left_grid_right_width_0_height_0_subtile_6__pin_inpad_0_[0] @@ -897,7 +886,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_15/in[3] set_disable_timing sb_0__1_/mux_bottom_track_17/in[2] set_disable_timing sb_0__1_/mux_bottom_track_23/in[0] set_disable_timing sb_0__1_/mux_bottom_track_19/in[0] -set_disable_timing sb_0__1_/mux_bottom_track_17/in[0] set_disable_timing sb_0__1_/mux_bottom_track_15/in[0] set_disable_timing sb_0__1_/mux_bottom_track_13/in[0] set_disable_timing sb_0__1_/mux_bottom_track_11/in[0] @@ -910,7 +898,6 @@ set_disable_timing sb_0__1_/mux_bottom_track_25/in[0] set_disable_timing sb_0__1_/mux_right_track_22/in[1] set_disable_timing sb_0__1_/mux_right_track_20/in[1] set_disable_timing sb_0__1_/mux_right_track_18/in[1] -set_disable_timing sb_0__1_/mux_right_track_16/in[2] set_disable_timing sb_0__1_/mux_right_track_14/in[2] set_disable_timing sb_0__1_/mux_right_track_12/in[3] set_disable_timing sb_0__1_/mux_right_track_10/in[2] @@ -924,12 +911,10 @@ set_disable_timing sb_0__1_/mux_right_track_24/in[2] # Disable timing for Switch block sb_1__0_ ################################################## set_disable_timing sb_1__0_/chany_top_in[0] -set_disable_timing sb_1__0_/chany_top_out[1] set_disable_timing sb_1__0_/chany_top_in[1] set_disable_timing sb_1__0_/chany_top_in[2] set_disable_timing sb_1__0_/chany_top_out[3] set_disable_timing sb_1__0_/chany_top_in[3] -set_disable_timing sb_1__0_/chany_top_out[4] set_disable_timing sb_1__0_/chany_top_in[4] set_disable_timing sb_1__0_/chany_top_out[5] set_disable_timing sb_1__0_/chany_top_in[5] @@ -965,7 +950,6 @@ set_disable_timing sb_1__0_/chanx_left_in[7] set_disable_timing sb_1__0_/chanx_left_out[7] set_disable_timing sb_1__0_/chanx_left_in[8] set_disable_timing sb_1__0_/chanx_left_out[8] -set_disable_timing sb_1__0_/chanx_left_in[9] set_disable_timing sb_1__0_/chanx_left_out[9] set_disable_timing sb_1__0_/chanx_left_in[10] set_disable_timing sb_1__0_/chanx_left_out[10] @@ -979,7 +963,6 @@ set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_3__pin_ set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -set_disable_timing sb_1__0_/top_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_1__0_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_O_0_[0] set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_1__0_/left_bottom_grid_top_width_0_height_0_subtile_1__pin_inpad_0_[0] @@ -1010,7 +993,6 @@ set_disable_timing sb_1__0_/mux_top_track_24/in[0] set_disable_timing sb_1__0_/mux_top_track_0/in[2] set_disable_timing sb_1__0_/mux_top_track_12/in[1] set_disable_timing sb_1__0_/mux_top_track_14/in[1] -set_disable_timing sb_1__0_/mux_top_track_2/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[2] set_disable_timing sb_1__0_/mux_top_track_16/in[1] set_disable_timing sb_1__0_/mux_left_track_1/in[1] @@ -1062,19 +1044,16 @@ set_disable_timing sb_1__0_/mux_top_track_16/in[2] set_disable_timing sb_1__0_/mux_top_track_14/in[3] set_disable_timing sb_1__0_/mux_top_track_12/in[2] set_disable_timing sb_1__0_/mux_top_track_10/in[2] -set_disable_timing sb_1__0_/mux_top_track_8/in[2] set_disable_timing sb_1__0_/mux_top_track_6/in[2] set_disable_timing sb_1__0_/mux_top_track_2/in[3] ################################################## # Disable timing for Switch block sb_1__1_ ################################################## set_disable_timing sb_1__1_/chany_bottom_out[0] -set_disable_timing sb_1__1_/chany_bottom_in[1] set_disable_timing sb_1__1_/chany_bottom_out[1] set_disable_timing sb_1__1_/chany_bottom_out[2] set_disable_timing sb_1__1_/chany_bottom_in[3] set_disable_timing sb_1__1_/chany_bottom_out[3] -set_disable_timing sb_1__1_/chany_bottom_in[4] set_disable_timing sb_1__1_/chany_bottom_out[4] set_disable_timing sb_1__1_/chany_bottom_in[5] set_disable_timing sb_1__1_/chany_bottom_out[5] @@ -1098,7 +1077,6 @@ set_disable_timing sb_1__1_/chanx_left_in[1] set_disable_timing sb_1__1_/chanx_left_in[2] set_disable_timing sb_1__1_/chanx_left_out[2] set_disable_timing sb_1__1_/chanx_left_in[3] -set_disable_timing sb_1__1_/chanx_left_out[3] set_disable_timing sb_1__1_/chanx_left_in[4] set_disable_timing sb_1__1_/chanx_left_out[4] set_disable_timing sb_1__1_/chanx_left_in[5] @@ -1107,7 +1085,6 @@ set_disable_timing sb_1__1_/chanx_left_in[6] set_disable_timing sb_1__1_/chanx_left_out[6] set_disable_timing sb_1__1_/chanx_left_in[7] set_disable_timing sb_1__1_/chanx_left_out[7] -set_disable_timing sb_1__1_/chanx_left_in[8] set_disable_timing sb_1__1_/chanx_left_out[8] set_disable_timing sb_1__1_/chanx_left_in[9] set_disable_timing sb_1__1_/chanx_left_out[9] @@ -1124,7 +1101,6 @@ set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_3__p set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_4__pin_inpad_0_[0] set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_5__pin_inpad_0_[0] set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_6__pin_inpad_0_[0] -set_disable_timing sb_1__1_/bottom_right_grid_left_width_0_height_0_subtile_7__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_[0] set_disable_timing sb_1__1_/left_top_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_[0] @@ -1185,7 +1161,6 @@ set_disable_timing sb_1__1_/mux_left_track_13/in[3] set_disable_timing sb_1__1_/mux_left_track_15/in[2] set_disable_timing sb_1__1_/mux_left_track_17/in[2] set_disable_timing sb_1__1_/mux_left_track_5/in[0] -set_disable_timing sb_1__1_/mux_left_track_7/in[0] set_disable_timing sb_1__1_/mux_left_track_9/in[0] set_disable_timing sb_1__1_/mux_left_track_11/in[0] set_disable_timing sb_1__1_/mux_left_track_13/in[0] @@ -1218,12 +1193,12 @@ set_disable_timing sb_1__1_/mux_bottom_track_23/in[1] ####################################### # Disable unused pins for pb_graph_node clb[0] ####################################### -set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[0] -set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[1] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[3] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[4] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[5] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[6] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[7] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[8] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_I[9] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_O[0] @@ -1234,8 +1209,8 @@ set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0/clb_clk[0] # Disable unused mux_inputs for pb_graph_node clb[0] ####################################### set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[0] -set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[1] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[2] +set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[3] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[4] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[5] set_disable_timing grid_clb_1__1_/logical_tile_clb_mode_clb__0//mux_fle_3_in_3/in[6] @@ -1564,31 +1539,31 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/* ####################################### set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[2][1][3] -####################################### -####################################### -# Disable unused pins for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/io_inpad[0] -####################################### -# Disable unused mux_inputs for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3//direct_interc_0_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] -####################################### -# Disable Timing for unused grid[2][1][4] +# Disable Timing for unused grid[2][1][3] ####################################### ####################################### # Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/* ####################################### # Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[2][1][4] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/io_inpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4//direct_interc_0_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__4/logical_tile_io_mode_physical__iopad_0/iopad_inpad[0] ####################################### # Disable Timing for unused grid[2][1][5] ####################################### @@ -1612,16 +1587,20 @@ set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/* ####################################### set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__6/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused grid[2][1][7] +# Disable Timing for unused resources in grid[2][1][7] ####################################### ####################################### -# Disable all the ports for pb_graph_node io[0] +# Disable unused pins for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/io_outpad[0] ####################################### -# Disable all the ports for pb_graph_node iopad[0] +# Disable unused mux_inputs for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_right_2__1_/logical_tile_io_mode_io__7/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for grid[1][0] ####################################### @@ -1728,46 +1707,42 @@ set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/* ####################################### set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__0/logical_tile_io_mode_physical__iopad_0/* ####################################### -# Disable Timing for unused resources in grid[0][1][1] -####################################### -####################################### -# Disable unused pins for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/io_outpad[0] -####################################### -# Disable unused mux_inputs for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] -####################################### -# Disable Timing for unused resources in grid[0][1][2] -####################################### -####################################### -# Disable unused pins for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/io_outpad[0] -####################################### -# Disable unused mux_inputs for pb_graph_node io[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2//direct_interc_1_/in[0] -####################################### -# Disable unused pins for pb_graph_node iopad[0] -####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] -####################################### -# Disable Timing for unused grid[0][1][3] +# Disable Timing for unused grid[0][1][1] ####################################### ####################################### # Disable all the ports for pb_graph_node io[0] ####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/* +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/* ####################################### # Disable all the ports for pb_graph_node iopad[0] ####################################### -set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/* +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__1/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused grid[0][1][2] +####################################### +####################################### +# Disable all the ports for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/* +####################################### +# Disable all the ports for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__2/logical_tile_io_mode_physical__iopad_0/* +####################################### +# Disable Timing for unused resources in grid[0][1][3] +####################################### +####################################### +# Disable unused pins for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/io_outpad[0] +####################################### +# Disable unused mux_inputs for pb_graph_node io[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3//direct_interc_1_/in[0] +####################################### +# Disable unused pins for pb_graph_node iopad[0] +####################################### +set_disable_timing grid_io_left_0__1_/logical_tile_io_mode_io__3/logical_tile_io_mode_physical__iopad_0/iopad_outpad[0] ####################################### # Disable Timing for unused grid[0][1][4] ####################################### diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v index b287ec87c..237dad23a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/and2_top_formal_verification.v @@ -42,14 +42,14 @@ wire [0:0] clk_fm; // ----- End Connect Global ports of FPGA top module ----- // ----- Link BLIF Benchmark I/Os to FPGA I/Os ----- -// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[26] ----- - assign gfpga_pad_GPIO_PAD_fm[26] = a[0]; +// ----- Blif Benchmark input a is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[27] ----- + assign gfpga_pad_GPIO_PAD_fm[27] = a[0]; -// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[25] ----- - assign gfpga_pad_GPIO_PAD_fm[25] = b[0]; +// ----- Blif Benchmark input b is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[15] ----- + assign gfpga_pad_GPIO_PAD_fm[15] = b[0]; -// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[11] ----- - assign c[0] = gfpga_pad_GPIO_PAD_fm[11]; +// ----- Blif Benchmark output c is mapped to FPGA IOPAD gfpga_pad_GPIO_PAD_fm[12] ----- + assign c[0] = gfpga_pad_GPIO_PAD_fm[12]; // ----- Wire unused FPGA I/Os to constants ----- assign gfpga_pad_GPIO_PAD_fm[0] = 1'b0; @@ -63,10 +63,9 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[8] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[9] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[10] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[12] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[11] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[13] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[14] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[15] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[16] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[17] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[18] = 1'b0; @@ -76,7 +75,8 @@ wire [0:0] clk_fm; assign gfpga_pad_GPIO_PAD_fm[22] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[23] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[24] = 1'b0; - assign gfpga_pad_GPIO_PAD_fm[27] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[25] = 1'b0; + assign gfpga_pad_GPIO_PAD_fm[26] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[28] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[29] = 1'b0; assign gfpga_pad_GPIO_PAD_fm[30] = 1'b0; @@ -125,14 +125,14 @@ initial begin force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_2.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_2_in_3.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = 4'b0001; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = 4'b1110; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_out[0:3] = {4{1'b1}}; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_0.mem_outb[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_1.mem_outb[0:3] = {4{1'b1}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_out[0:3] = {4{1'b0}}; force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_2.mem_outb[0:3] = {4{1'b1}}; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0011; - force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1100; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_out[0:3] = 4'b0111; + force U0_formal_verification.grid_clb_1__1_.logical_tile_clb_mode_clb__0.mem_fle_3_in_3.mem_outb[0:3] = 4'b1000; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__0.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_top_1__2_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -155,10 +155,10 @@ initial begin force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__1.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__2.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; - force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__3.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b0; + force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__4.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__5.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_right_2__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; @@ -197,14 +197,14 @@ initial begin force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__6.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_out[0] = 1'b1; force U0_formal_verification.grid_io_left_0__1_.logical_tile_io_mode_io__7.logical_tile_io_mode_physical__iopad_0.GPIO_DFF_mem.mem_outb[0] = 1'b0; - force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = 3'b011; - force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = 3'b100; - force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = 2'b01; - force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = 2'b10; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_out[0:1] = {2{1'b0}}; + force U0_formal_verification.sb_0__0_.mem_top_track_2.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_4.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; @@ -241,8 +241,8 @@ initial begin force U0_formal_verification.sb_0__0_.mem_right_track_14.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__0_.mem_right_track_18.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__0_.mem_right_track_20.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__0_.mem_right_track_22.mem_out[0:1] = {2{1'b1}}; @@ -265,8 +265,8 @@ initial begin force U0_formal_verification.sb_0__1_.mem_right_track_12.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_14.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_0__1_.mem_right_track_16.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_right_track_18.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_right_track_20.mem_out[0:1] = {2{1'b0}}; @@ -291,8 +291,8 @@ initial begin force U0_formal_verification.sb_0__1_.mem_bottom_track_13.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_15.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_0__1_.mem_bottom_track_17.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_19.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_0__1_.mem_bottom_track_21.mem_out[0:1] = {2{1'b1}}; @@ -303,14 +303,14 @@ initial begin force U0_formal_verification.sb_0__1_.mem_bottom_track_25.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_out[0:2] = {3{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_0.mem_outb[0:2] = {3{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_out[0:2] = 3'b001; + force U0_formal_verification.sb_1__0_.mem_top_track_2.mem_outb[0:2] = 3'b110; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_out[0:1] = 2'b10; force U0_formal_verification.sb_1__0_.mem_top_track_4.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_6.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_out[0:1] = 2'b10; + force U0_formal_verification.sb_1__0_.mem_top_track_8.mem_outb[0:1] = 2'b01; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__0_.mem_top_track_10.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__0_.mem_top_track_12.mem_out[0:1] = {2{1'b0}}; @@ -385,8 +385,8 @@ initial begin force U0_formal_verification.sb_1__1_.mem_left_track_3.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_5.mem_outb[0:1] = {2{1'b1}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b0}}; - force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_out[0:1] = {2{1'b1}}; + force U0_formal_verification.sb_1__1_.mem_left_track_7.mem_outb[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_out[0:1] = {2{1'b0}}; force U0_formal_verification.sb_1__1_.mem_left_track_9.mem_outb[0:1] = {2{1'b1}}; force U0_formal_verification.sb_1__1_.mem_left_track_11.mem_out[0:1] = {2{1'b0}}; @@ -443,16 +443,16 @@ initial begin force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_bottom_ipin_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_out[0:2] = 3'b110; + force U0_formal_verification.cbx_1__1_.mem_top_ipin_0.mem_outb[0:2] = 3'b001; force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cbx_1__1_.mem_top_ipin_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = 3'b101; - force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = 3'b010; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_0__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_0__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; @@ -475,18 +475,18 @@ initial begin force U0_formal_verification.cby_1__1_.mem_left_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_2.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_out[0:2] = {3{1'b0}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_3.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_out[0:2] = 3'b101; + force U0_formal_verification.cby_1__1_.mem_left_ipin_4.mem_outb[0:2] = 3'b010; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_5.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_6.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_left_ipin_7.mem_outb[0:2] = {3{1'b1}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b0}}; - force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_out[0:2] = {3{1'b1}}; + force U0_formal_verification.cby_1__1_.mem_right_ipin_0.mem_outb[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_out[0:2] = {3{1'b0}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_1.mem_outb[0:2] = {3{1'b1}}; force U0_formal_verification.cby_1__1_.mem_right_ipin_2.mem_out[0:2] = {3{1'b0}}; diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit index 5127c7105..7ed88111a 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.bit @@ -3,7 +3,7 @@ // Bitstream width (LSB -> MSB): 1 1 1 -0 +1 0 0 0 @@ -14,9 +14,9 @@ 0 0 1 -0 -0 -0 +1 +1 +1 0 0 0 @@ -143,12 +143,9 @@ 0 0 0 -0 -0 -0 -0 -0 -0 +1 +1 +1 0 0 0 @@ -159,9 +156,8 @@ 0 0 1 -1 -1 0 +1 0 0 0 @@ -261,6 +257,9 @@ 0 1 1 +0 +0 +1 1 1 1 @@ -270,39 +269,6 @@ 1 1 1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -1 -0 -1 -1 -1 -1 -0 -0 -1 1 0 0 @@ -336,32 +302,10 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -1 -0 1 1 0 0 -0 -0 -0 1 1 0 @@ -405,80 +349,136 @@ 0 0 0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -1 -1 -1 -1 -1 -1 -1 -1 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 -0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 1 1 0 @@ -515,7 +515,6 @@ 1 1 1 -1 0 1 1 @@ -528,3 +527,4 @@ 1 1 1 +1 diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml index 558580484..419917847 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_bitstream.xml @@ -10,7 +10,7 @@ - + @@ -32,11 +32,11 @@ - + - + - + @@ -290,11 +290,11 @@ - + - + - + @@ -314,17 +314,17 @@ - + - + - + - + - + @@ -506,7 +506,7 @@ - + @@ -516,7 +516,7 @@ - + @@ -592,17 +592,17 @@ - + - + - + - + - + @@ -616,9 +616,9 @@ - + - + @@ -702,21 +702,21 @@ - + - + - + - + - + @@ -736,9 +736,9 @@ - + - + @@ -796,7 +796,7 @@ - + @@ -864,9 +864,9 @@ - + - + @@ -954,9 +954,9 @@ - + - + @@ -1034,9 +1034,9 @@ - + - + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml index 1b97176e2..eddb1a906 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/fabric_independent_bitstream.xml @@ -431,14 +431,14 @@ - - + + - + - + @@ -449,10 +449,10 @@ - - - - + + + + @@ -498,14 +498,14 @@ - - + + - + - + @@ -516,9 +516,9 @@ - + - + @@ -715,7 +715,7 @@ - + @@ -731,7 +731,7 @@ - + @@ -1054,17 +1054,17 @@ - + - + - + - - + + @@ -1074,16 +1074,16 @@ - - + + - + - + - + @@ -1093,8 +1093,8 @@ - - + + @@ -1112,16 +1112,16 @@ - + - + - - - + + + @@ -1190,7 +1190,7 @@ - + @@ -1209,7 +1209,7 @@ - + @@ -1228,7 +1228,7 @@ - + @@ -1480,15 +1480,15 @@ - + - + - - - + + + @@ -1713,13 +1713,13 @@ - + - + - - + + @@ -1749,7 +1749,7 @@ - + @@ -1767,7 +1767,7 @@ - + @@ -1826,7 +1826,7 @@ - + @@ -1846,8 +1846,8 @@ - - + + @@ -1865,8 +1865,8 @@ - - + + @@ -1884,7 +1884,7 @@ - + @@ -1961,16 +1961,16 @@ - - + + - + - - - + + + @@ -1981,7 +1981,7 @@ - + @@ -1999,7 +1999,7 @@ - + @@ -2077,16 +2077,16 @@ - + - + - + - + @@ -2136,13 +2136,13 @@ - + - + - - + + @@ -2193,7 +2193,7 @@ - + @@ -2213,7 +2213,7 @@ - + @@ -2559,7 +2559,7 @@ - + @@ -2675,7 +2675,7 @@ - + @@ -2695,8 +2695,8 @@ - - + + @@ -2845,7 +2845,7 @@ - + @@ -2869,11 +2869,11 @@ - + - - - + + + @@ -2902,7 +2902,7 @@ - + @@ -3128,7 +3128,7 @@ - + @@ -3266,7 +3266,7 @@ - + @@ -3287,7 +3287,7 @@ - + @@ -3360,7 +3360,7 @@ - + @@ -3382,7 +3382,7 @@ - + @@ -3403,7 +3403,7 @@ - + @@ -3498,15 +3498,15 @@ - + - + - - - + + + @@ -3519,7 +3519,7 @@ - + @@ -3541,7 +3541,7 @@ - + @@ -3565,7 +3565,7 @@ - + @@ -3573,12 +3573,12 @@ - + - - - - + + + + @@ -3588,20 +3588,20 @@ - + - + - + - - + + - + @@ -3611,12 +3611,12 @@ - + - + @@ -3636,7 +3636,7 @@ - + @@ -3657,7 +3657,7 @@ - + @@ -3726,7 +3726,7 @@ - + @@ -3749,12 +3749,12 @@ - + - + @@ -3775,7 +3775,7 @@ - + @@ -3822,7 +3822,7 @@ - + @@ -3843,7 +3843,7 @@ - + @@ -3874,12 +3874,12 @@ - + - - - - + + + + @@ -3891,18 +3891,18 @@ - + - + - - + + - + @@ -3912,7 +3912,7 @@ - + @@ -3981,7 +3981,7 @@ - + @@ -3989,12 +3989,12 @@ - + - - - - + + + + diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc index 15b7bb175..7b26126b2 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/global_ports.sdc @@ -14,7 +14,7 @@ set_units -time s ################################################## # Create clock ################################################## -create_clock -name clk[0] -period 1.148903084e-09 -waveform {0 5.744515419e-10} [get_ports {clk[0]}] +create_clock -name clk[0] -period 1.525308102e-09 -waveform {0 7.62654051e-10} [get_ports {clk[0]}] ################################################## # Create programmable clock ################################################## diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml index 8a17b9176..e39c498fe 100644 --- a/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml +++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/device_1x1/golden_outputs_no_time_stamp/pin_mapping.xml @@ -3,7 +3,7 @@ --> - - - + + +