From 5f6050d40474c9a55f61828eb2d705134966b895 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 18 Aug 2023 21:48:40 -0700
Subject: [PATCH] [test] add a new test to validate combo: group tile, tile
 annotation and subtile

---
 .../regression_test_scripts/basic_reg_test.sh |  1 +
 .../config/task.conf                          | 42 +++++++++++++++++++
 .../config/tile_config.xml                    |  1 +
 3 files changed, 44 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf
 create mode 100644 openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml

diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
index 16845c00f..4ec35395f 100755
--- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh
+++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh
@@ -179,6 +179,7 @@ run-task basic_tests/tile_organization/io_subtile_strong $@
 echo -e "Testing tile grouping on a homogeneous FPGA fabric (Full testbench)";
 run-task basic_tests/tile_organization/homo_fabric_tile $@
 echo -e "Testing tile grouping on a homogeneous FPGA fabric (Preconfigured testbench)";
+run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile $@
 run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
 run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
 run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf
new file mode 100644
index 000000000..1c477f704
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/task.conf
@@ -0,0 +1,42 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_preconfig_testbench_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_vpr_extra_options=
+openfpga_pb_pin_fixup_command=
+openfpga_vpr_device=2x2_hybrid_io
+openfpga_vpr_route_chan_width=20
+openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
+openfpga_verilog_testbench_options=--explicit_port_mapping
+
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
+
+[SYNTHESIS_PARAM]
+bench_read_verilog_options_common = -nolatches
+bench0_top = and2_pipelined
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml
new file mode 100644
index 000000000..1a1f3f6e8
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile/config/tile_config.xml
@@ -0,0 +1 @@
+<tiles style="top_left"/>