From 5f4e7dc5d413fc143c64e91b451f7eb30a732516 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 5 Apr 2020 16:52:21 -0600 Subject: [PATCH] support gpinput and gpoutput ports in module manager and circuit library --- .../libarchopenfpga/src/circuit_library.cpp | 16 ++ .../libarchopenfpga/src/circuit_library.h | 4 + .../src/read_xml_circuit_library.cpp | 7 + openfpga/src/fabric/module_manager.cpp | 2 +- openfpga/src/fabric/module_manager.h | 3 +- .../fpga_verilog/verilog_module_writer.cpp | 3 +- .../src/fpga_verilog/verilog_writer_utils.cpp | 9 +- openfpga/src/utils/module_manager_utils.cpp | 188 +++++++----------- .../k6_frac_N10_spyio_40nm_openfpga.xml | 2 + 9 files changed, 107 insertions(+), 127 deletions(-) diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index 0ea7139df..cf8b8714f 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -892,6 +892,12 @@ size_t CircuitLibrary::port_default_value(const CircuitPortId& circuit_port_id) return port_default_values_[circuit_port_id]; } +/* Return a flag if the port is used in mode-selection purpuse of a circuit model */ +bool CircuitLibrary::port_is_io(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_io_[circuit_port_id]; +} /* Return a flag if the port is used in mode-selection purpuse of a circuit model */ bool CircuitLibrary::port_is_mode_select(const CircuitPortId& circuit_port_id) const { @@ -1344,6 +1350,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_lib_names_.emplace_back(); port_inv_prefix_.emplace_back(); port_default_values_.push_back(-1); + port_is_io_.push_back(false); port_is_mode_select_.push_back(false); port_is_global_.push_back(false); port_is_reset_.push_back(false); @@ -1414,6 +1421,15 @@ void CircuitLibrary::set_port_default_value(const CircuitPortId& circuit_port_id return; } +/* Set the is_mode_select for a port of a circuit model */ +void CircuitLibrary::set_port_is_io(const CircuitPortId& circuit_port_id, + const bool& is_io) { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_io_[circuit_port_id] = is_io; + return; +} + /* Set the is_mode_select for a port of a circuit model */ void CircuitLibrary::set_port_is_mode_select(const CircuitPortId& circuit_port_id, const bool& is_mode_select) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index 8f2781349..c6a62dc27 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -275,6 +275,7 @@ class CircuitLibrary { std::string port_lib_name(const CircuitPortId& circuit_port_id) const; std::string port_inv_prefix(const CircuitPortId& circuit_port_id) const; size_t port_default_value(const CircuitPortId& circuit_port_id) const; + bool port_is_io(const CircuitPortId& circuit_port_id) const; bool port_is_mode_select(const CircuitPortId& circuit_port_id) const; bool port_is_global(const CircuitPortId& circuit_port_id) const; bool port_is_reset(const CircuitPortId& circuit_port_id) const; @@ -346,6 +347,8 @@ class CircuitLibrary { const std::string& inv_prefix); void set_port_default_value(const CircuitPortId& circuit_port_id, const size_t& default_val); + void set_port_is_io(const CircuitPortId& circuit_port_id, + const bool& is_io); void set_port_is_mode_select(const CircuitPortId& circuit_port_id, const bool& is_mode_select); void set_port_is_global(const CircuitPortId& circuit_port_id, @@ -529,6 +532,7 @@ class CircuitLibrary { vtr::vector port_lib_names_; vtr::vector port_inv_prefix_; vtr::vector port_default_values_; + vtr::vector port_is_io_; vtr::vector port_is_mode_select_; vtr::vector port_is_global_; vtr::vector port_is_reset_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index af12297d1..cd8ffd1c5 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -486,6 +486,13 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Parse the port size, by default it will be 1 */ circuit_lib.set_port_size(port, get_attribute(xml_port, "size", loc_data).as_int(1)); + /* Identify if the port is for io, this is only applicable to INPUT ports. + * By default, it will NOT be a mode selection port + */ + if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) { + circuit_lib.set_port_is_io(port, get_attribute(xml_port, "io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + } + /* Identify if the port is for mode selection, this is only applicable to SRAM ports. * By default, it will NOT be a mode selection port */ diff --git a/openfpga/src/fabric/module_manager.cpp b/openfpga/src/fabric/module_manager.cpp index 7f444318e..d03af54b0 100644 --- a/openfpga/src/fabric/module_manager.cpp +++ b/openfpga/src/fabric/module_manager.cpp @@ -120,7 +120,7 @@ std::string ModuleManager::module_name(const ModuleId& module_id) const { /* Get the string of a module port type */ std::string ModuleManager::module_port_type_str(const enum e_module_port_type& port_type) const { - std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "SPY PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; + std::array MODULE_PORT_TYPE_STRING = {{"GLOBAL PORTS", "GPIN PORTS", "GPOUT PORTS", "GPIO PORTS", "INOUT PORTS", "INPUT PORTS", "OUTPUT PORTS", "CLOCK PORTS"}}; return MODULE_PORT_TYPE_STRING[port_type]; } diff --git a/openfpga/src/fabric/module_manager.h b/openfpga/src/fabric/module_manager.h index 1bfbd8b49..cd79bde8c 100644 --- a/openfpga/src/fabric/module_manager.h +++ b/openfpga/src/fabric/module_manager.h @@ -28,7 +28,8 @@ class ModuleManager { public: /* Private data structures */ enum e_module_port_type { MODULE_GLOBAL_PORT, /* Global inputs */ - MODULE_SPY_PORT, /* Global outputs, which is designed for spypads */ + MODULE_GPIN_PORT, /* General-purpose input */ + MODULE_GPOUT_PORT, /* General-purpose outputs, could be used for spypads */ MODULE_GPIO_PORT, /* General-purpose IOs, which are data IOs of the fabric */ MODULE_INOUT_PORT, /* Normal (non-global) inout ports */ MODULE_INPUT_PORT, /* Normal (non-global) input ports */ diff --git a/openfpga/src/fpga_verilog/verilog_module_writer.cpp b/openfpga/src/fpga_verilog/verilog_module_writer.cpp index 0d6103beb..7d6883236 100644 --- a/openfpga/src/fpga_verilog/verilog_module_writer.cpp +++ b/openfpga/src/fpga_verilog/verilog_module_writer.cpp @@ -396,7 +396,8 @@ void write_verilog_instance_to_file(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index b771f4752..90ee95e9c 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -129,7 +129,8 @@ void print_verilog_module_definition(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; @@ -189,7 +190,8 @@ void print_verilog_module_ports(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_INPUT; - port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_OUTPUT; + port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_INPUT; + port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_OUTPUT; port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_INOUT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_INOUT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_INPUT; @@ -346,7 +348,8 @@ void print_verilog_module_instance(std::fstream& fp, /* port type2type mapping */ std::map port_type2type_map; port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT; - port_type2type_map[ModuleManager::MODULE_SPY_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPIN_PORT] = VERILOG_PORT_CONKT; + port_type2type_map[ModuleManager::MODULE_GPOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT; port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT; diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 8806003b7..3c1ef2de2 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -42,13 +42,17 @@ ModuleId add_circuit_model_to_module_manager(ModuleManager& module_manager, */ for (const auto& port : circuit_lib.model_global_ports(circuit_model, false)) { BasicPort port_info(circuit_lib.port_prefix(port), circuit_lib.port_size(port)); - if (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) { + if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) + && (false == circuit_lib.port_is_io(port)) ) { module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); } else if (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(port)) { module_manager.add_port(module, port_info, ModuleManager::MODULE_GLOBAL_PORT); + } else if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) + && (false == circuit_lib.port_is_io(port)) ) { + module_manager.add_port(module, port_info, ModuleManager::MODULE_GPIN_PORT); } else { VTR_ASSERT(CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)); - module_manager.add_port(module, port_info, ModuleManager::MODULE_SPY_PORT); + module_manager.add_port(module, port_info, ModuleManager::MODULE_GPOUT_PORT); } } @@ -931,19 +935,35 @@ size_t find_module_num_config_bits(const ModuleManager& module_manager, } /******************************************************************** - * Add GPIO ports to the module: + * Add General purpose I/O ports to the module: * In this function, the following tasks are done: - * 1. find all the GPIO ports from the child modules and build a list of it, - * 2. Merge all the GPIO ports with the same name + * 1. find all the I/O ports from the child modules and build a list of it, + * 2. Merge all the I/O ports with the same name * 3. add the ports to the pb_module * 4. add module nets to connect to the GPIO ports of each sub module + * + * Module + * ----------------------+ + * | + * child[0] | + * -----------+ | + * |----------+----> outputA[0] + * -----------+ | + * | + * child[1] | + * -----------+ | + * |----------+----> outputA[1] + * -----------+ | + * * Note: This function should be call ONLY after all the sub modules (instances) * have been added to the pb_module! * Otherwise, some GPIO ports of the sub modules may be missed! *******************************************************************/ -void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id) { +static +void add_module_io_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id, + const ModuleManager::e_module_port_type& module_port_type) { std::vector gpio_ports_to_add; /* Iterate over the child modules */ @@ -951,7 +971,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, /* Iterate over the child instances */ for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { /* Find all the global ports, whose port type is special */ - for (BasicPort gpio_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { + for (BasicPort gpio_port : module_manager.module_ports_by_type(child, module_port_type)) { /* If this port is not mergeable, we update the list */ bool is_mergeable = false; for (BasicPort& gpio_port_to_add : gpio_ports_to_add) { @@ -979,7 +999,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, std::vector gpio_port_ids; /* Add the gpio ports for the module */ for (const BasicPort& gpio_port_to_add : gpio_ports_to_add) { - ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, ModuleManager::MODULE_GPIO_PORT); + ModulePortId port_id = module_manager.add_port(module_id, gpio_port_to_add, module_port_type); gpio_port_ids.push_back(port_id); } @@ -990,7 +1010,7 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, /* Iterate over the child instances */ for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { /* Find all the global ports, whose port type is special */ - for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_GPIO_PORT)) { + for (ModulePortId child_gpio_port_id : module_manager.module_port_ids_by_type(child, module_port_type)) { BasicPort child_gpio_port = module_manager.module_port(child, child_gpio_port_id); /* Find the port with the same name! */ for (size_t iport = 0; iport < gpio_ports_to_add.size(); ++iport) { @@ -1001,8 +1021,22 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, for (const size_t& pin_id : child_gpio_port.pins()) { /* Reach here, it means this is the port we want, create a net and configure its source and sink */ ModuleNetId net = module_manager.create_module_net(module_id); - module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); - module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); + /* - For GPIO and GPIN ports + * the source of the net is the current module + * the sink of the net is the child module + * - For GPOUT ports + * the source of the net is the child module + * the sink of the net is the current module + */ + if ( (ModuleManager::MODULE_GPIO_PORT == module_port_type) + || (ModuleManager::MODULE_GPIN_PORT == module_port_type) ) { + module_manager.add_module_net_source(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); + module_manager.add_module_net_sink(module_id, net, child, child_instance, child_gpio_port_id, pin_id); + } else { + VTR_ASSERT(ModuleManager::MODULE_GPOUT_PORT == module_port_type); + module_manager.add_module_net_sink(module_id, net, module_id, 0, gpio_port_ids[iport], gpio_port_lsb[iport]); + module_manager.add_module_net_source(module_id, net, child, child_instance, child_gpio_port_id, pin_id); + } /* Update the LSB counter */ gpio_port_lsb[iport]++; } @@ -1020,6 +1054,27 @@ void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, } } +/******************************************************************** + * Add GPIO ports to the module: + * In this function, the following tasks are done: + * 1. find all the GPIO ports from the child modules and build a list of it, + * 2. Merge all the GPIO ports with the same name + * 3. add the ports to the pb_module + * 4. add module nets to connect to the GPIO ports of each sub module + * + * Note: This function should be call ONLY after all the sub modules (instances) + * have been added to the pb_module! + * Otherwise, some GPIO ports of the sub modules may be missed! + *******************************************************************/ +void add_module_gpio_ports_from_child_modules(ModuleManager& module_manager, + const ModuleId& module_id) { + add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIO_PORT); + + add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPIN_PORT); + + add_module_io_ports_from_child_modules(module_manager, module_id, ModuleManager::MODULE_GPOUT_PORT); +} + /******************************************************************** * Add global input ports to the module: * In this function, the following tasks are done: @@ -1100,112 +1155,6 @@ void add_module_global_input_ports_from_child_modules(ModuleManager& module_mana } } -/******************************************************************** - * Add global output ports to the module: - * In this function, the following tasks are done: - * 1. find all the global output ports from the child modules and build a list of it, - * 2. add the output ports to the pb_module - * 3. add the module nets to connect the pb_module global ports to those of child modules - * - * Module - * ----------------------+ - * | - * child[0] | - * -----------+ | - * |----------+----> outputA[0] - * -----------+ | - * | - * child[1] | - * -----------+ | - * |----------+----> outputA[1] - * -----------+ | - * - * Note: This function should be call ONLY after all the sub modules (instances) - * have been added to the pb_module! - * Otherwise, some global ports of the sub modules may be missed! - *******************************************************************/ -void add_module_global_output_ports_from_child_modules(ModuleManager& module_manager, - const ModuleId& module_id) { - std::vector global_ports_to_add; - std::vector global_port_names; - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (size_t i = 0; i < module_manager.num_instance(module_id, child); ++i) { - /* Find all the global ports, whose port type is special */ - for (BasicPort global_port : module_manager.module_ports_by_type(child, ModuleManager::MODULE_SPY_PORT)) { - /* Search in the global port list to be added, if this is unique, we update the list */ - std::vector::iterator it = std::find(global_port_names.begin(), global_port_names.end(), global_port.get_name()); - if (it != global_port_names.end()) { - /* Found in the global port with the same name, increase the port size */ - global_ports_to_add[it - global_port_names.begin()].expand(global_port.get_width()); - continue; /* Finish for the port already in the list */ - } - /* Reach here, this is an unique global port, update the list */ - global_ports_to_add.push_back(global_port); - global_port_names.push_back(global_port.get_name()); - } - } - } - - /* Record the port id for each type of global port */ - std::vector global_port_ids; - /* Add the global ports for the module */ - for (const BasicPort& global_port_to_add : global_ports_to_add) { - ModulePortId port_id = module_manager.add_port(module_id, global_port_to_add, ModuleManager::MODULE_SPY_PORT); - global_port_ids.push_back(port_id); - } - - /* Add module nets to connect the global ports of the module to the global ports of the sub module */ - /* Create a counter for each global port to record the current LSB */ - std::vector global_port_lsbs(global_port_ids.size(), 0); - - /* Iterate over the child modules */ - for (const ModuleId& child : module_manager.child_modules(module_id)) { - /* Iterate over the child instances */ - for (const size_t& child_instance : module_manager.child_module_instances(module_id, child)) { - /* Find all the global ports, whose port type is special */ - for (ModulePortId child_global_port_id : module_manager.module_port_ids_by_type(child, ModuleManager::MODULE_SPY_PORT)) { - /* Find the global port from the child module */ - BasicPort child_global_port = module_manager.module_port(child, child_global_port_id); - /* Search in the global port list to be added, find the port id */ - std::vector::iterator it = std::find(global_port_names.begin(), global_port_names.end(), child_global_port.get_name()); - VTR_ASSERT(it != global_port_names.end()); - - /* Find the global port from the parent module */ - size_t module_global_port_offset = it - global_port_names.begin(); - ModulePortId module_global_port_id = global_port_ids[module_global_port_offset]; - BasicPort module_global_port = module_manager.module_port(module_id, module_global_port_id); - /* Current LSB should be in range */ - VTR_ASSERT(module_global_port.get_width() > global_port_lsbs[module_global_port_offset]); - /* Set the global port from the parent module as the LSB recorded */ - module_global_port.set_width(global_port_lsbs[module_global_port_offset], global_port_lsbs[module_global_port_offset] + child_global_port.get_width() - 1); - /* Update the LSB */ - global_port_lsbs[module_global_port_offset] += child_global_port.get_width(); - - /* The global ports should match in size */ - VTR_ASSERT(module_global_port.get_width() == child_global_port.get_width()); - /* For each pin of the child port, create a net and do wiring */ - for (size_t pin_id = 0; pin_id < child_global_port.pins().size(); ++pin_id) { - /* Reach here, it means this is the port we want, create a net and configure its source and sink */ - ModuleNetId net = module_manager.create_module_net(module_id); - module_manager.add_module_net_source(module_id, net, child, child_instance, child_global_port_id, child_global_port.pins()[pin_id]); - module_manager.add_module_net_sink(module_id, net, module_id, 0, module_global_port_id, module_global_port.pins()[pin_id]); - /* We finish for this child gpio port */ - } - } - } - } - - /* Find check: all the LSBs of global ports should match the MSB */ - for (size_t iport = 0; iport < global_port_ids.size(); ++iport) { - BasicPort module_global_port = module_manager.module_port(module_id, global_port_ids[iport]); - if (module_global_port.get_width() != global_port_lsbs[iport]) - VTR_ASSERT(module_global_port.get_width() == global_port_lsbs[iport]); - } -} - /******************************************************************** * Add global ports to the module: * In this function, we will add global input ports and global output ports @@ -1228,9 +1177,6 @@ void add_module_global_ports_from_child_modules(ModuleManager& module_manager, const ModuleId& module_id) { /* Input ports */ add_module_global_input_ports_from_child_modules(module_manager, module_id); - - /* Output ports */ - add_module_global_output_ports_from_child_modules(module_manager, module_id); } /******************************************************************** diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9d81c5b3e..b8f5fc249 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -181,6 +181,8 @@ + +