refactored analysis SDC generation for switch blocks
This commit is contained in:
tangxifan
parent
876733f052
commit
5f219b428c
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@ -37,6 +37,84 @@ bool is_rr_node_to_be_disable_for_analysis(t_rr_node* cur_rr_node) {
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return true;
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return true;
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}
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}
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/********************************************************************
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* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
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* Here, we start from each input of a routing module, and traverse forward to the sink
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* port of the module net whose source is the input
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* We will find the instance name which is the parent of the sink port, and search the
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* net id through the instance_name_to_net_map
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* The the net id does not match the net id of this input, we will disable the sink port!
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*
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* parent_module
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* +-----------------------
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* | MUX instance A
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* | +-----------
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* input_port--->|--+---x-->| sink port (disable! net_id = Y)
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* (net_id = X) | | +----------
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* | | MUX instance B
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* | | +----------
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* | +------>| sink port (do not disable! net_id = X)
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*
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*******************************************************************/
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static
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void disable_analysis_module_input_port_net_sinks(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const std::string& parent_instance_name,
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const ModulePortId& module_input_port,
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t_rr_node* input_rr_node,
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const std::map<std::string, int> mux_instance_to_net_map) {
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/* Validate file stream */
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check_file_handler(fp);
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/* Find the module net which sources from this port! */
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for (const size_t& pin : module_manager.module_port(parent_module, module_input_port).pins()) {
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ModuleNetId module_net = module_manager.module_instance_port_net(parent_module, parent_module, 0, module_input_port, pin);
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VTR_ASSERT(true == module_manager.valid_module_net_id(parent_module, module_net));
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/* Touch each sink of the net! */
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for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(parent_module, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(parent_module, module_net)[sink_id];
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size_t sink_instance = module_manager.net_sink_instances(parent_module, module_net)[sink_id];
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/* Skip when sink module is the parent module,
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* the output ports of parent modules have been disabled/enabled already!
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*/
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if (sink_module == parent_module) {
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continue;
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}
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std::string sink_instance_name = module_manager.instance_name(parent_module, sink_module, sink_instance);
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bool disable_timing = false;
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/* Check if this node is used by benchmark */
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if (true == is_rr_node_to_be_disable_for_analysis(input_rr_node)) {
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/* Disable all the sinks! */
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disable_timing = true;
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} else {
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/* See if the net id matches. If does not match, we should disable! */
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if (input_rr_node->vpack_net_num != mux_instance_to_net_map.at(sink_instance_name)) {
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disable_timing = true;
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}
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}
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/* Time to write SDC command to disable timing or not */
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if (false == disable_timing) {
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continue;
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}
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(parent_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(parent_module, module_net)[sink_id],
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module_manager.net_sink_pins(parent_module, module_net)[sink_id]);
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << parent_instance_name << "/";
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fp << sink_instance_name << "/";
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fp << generate_sdc_port(sink_port);
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fp << std::endl;
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}
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}
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}
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/********************************************************************
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/********************************************************************
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* This function will disable
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* This function will disable
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* 1. all the unused port (unmapped by a benchmark) of a connection block
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* 1. all the unused port (unmapped by a benchmark) of a connection block
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@ -150,6 +228,11 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
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enum e_side cb_ipin_side = cb_sides[side];
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enum e_side cb_ipin_side = cb_sides[side];
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
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for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
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t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
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t_rr_node* ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
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/* Find the MUX instance that drives the IPIN! */
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std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string(""));
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mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num;
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if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) {
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if (false == is_rr_node_to_be_disable_for_analysis(ipin_node)) {
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continue;
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continue;
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}
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}
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@ -157,10 +240,6 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
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continue;
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continue;
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}
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}
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/* Find the MUX instance that drives the IPIN! */
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std::string mux_instance_name = generate_cb_mux_instance_name(CONNECTION_BLOCK_MUX_INSTANCE_PREFIX, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), inode, std::string(""));
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mux_instance_to_net_map[mux_instance_name] = ipin_node->vpack_net_num;
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vtr::Point<size_t> port_coord(ipin_node->xlow, ipin_node->ylow);
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vtr::Point<size_t> port_coord(ipin_node->xlow, ipin_node->ylow);
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std::string port_name = generate_grid_side_port_name(grids,
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std::string port_name = generate_grid_side_port_name(grids,
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port_coord,
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port_coord,
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@ -229,52 +308,12 @@ void print_analysis_sdc_disable_cb_unused_resources(std::fstream& fp,
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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ModulePortId module_port = module_manager.find_module_port(cb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, module_port));
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/* Find the module net which sources from this port! */
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disable_analysis_module_input_port_net_sinks(fp,
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for (const size_t& pin : module_manager.module_port(cb_module, module_port).pins()) {
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module_manager, cb_module,
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ModuleNetId module_net = module_manager.module_instance_port_net(cb_module, cb_module, 0, module_port, pin);
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cb_instance_name,
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VTR_ASSERT(true == module_manager.valid_module_net_id(cb_module, module_net));
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module_port,
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chan_node,
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/* Touch each sink of the net! */
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mux_instance_to_net_map);
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for (const ModuleNetSinkId& sink_id : module_manager.module_net_sinks(cb_module, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(cb_module, module_net)[sink_id];
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size_t sink_instance = module_manager.net_sink_instances(cb_module, module_net)[sink_id];
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/* Skip when sink module is the cb module,
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* the output ports of cb modules have been disabled/enabled already!
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*/
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if (sink_module == cb_module) {
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continue;
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}
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std::string sink_instance_name = module_manager.instance_name(cb_module, sink_module, sink_instance);
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bool disable_timing = false;
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/* Check if this node is used by benchmark */
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if (true == is_rr_node_to_be_disable_for_analysis(chan_node)) {
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/* Disable all the sinks! */
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disable_timing = true;
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} else {
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/* See if the net id matches. If does not match, we should disable! */
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if (chan_node->vpack_net_num != mux_instance_to_net_map[sink_instance_name]) {
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disable_timing = true;
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}
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}
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/* Time to write SDC command to disable timing or not */
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if (false == disable_timing) {
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continue;
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}
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BasicPort sink_port = module_manager.module_port(sink_module, module_manager.net_sink_ports(cb_module, module_net)[sink_id]);
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sink_port.set_width(module_manager.net_sink_pins(cb_module, module_net)[sink_id],
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module_manager.net_sink_pins(cb_module, module_net)[sink_id]);
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/* Get the input id that is used! Disable the unused inputs! */
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fp << "set_disable_timing ";
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fp << cb_instance_name << "/";
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fp << sink_instance_name << "/";
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fp << generate_sdc_port(sink_port);
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fp << std::endl;
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}
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}
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}
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}
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}
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}
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@ -332,3 +371,275 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
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CHANY, compact_routing_hierarchy);
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CHANY, compact_routing_hierarchy);
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}
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}
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/********************************************************************
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* This function will disable
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* 1. all the unused port (unmapped by a benchmark) of a switch block
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* 2. all the unused inputs (unmapped by a benchmark) of routing multiplexers
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* in a switch block
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*******************************************************************/
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static
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void print_analysis_sdc_disable_sb_unused_resources(std::fstream& fp,
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const std::vector<std::vector<t_grid_tile>>& grids,
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const ModuleManager& module_manager,
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const DeviceRRGSB& L_device_rr_gsb,
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const RRGSB& rr_gsb,
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const bool& compact_routing_hierarchy) {
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/* Validate file stream */
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check_file_handler(fp);
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vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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std::string sb_instance_name = generate_switch_block_module_name(gsb_coordinate);
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/* If we use the compact routing hierarchy, we need to find the module name !*/
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vtr::Point<size_t> sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
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if (true == compact_routing_hierarchy) {
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DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord);
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sb_coordinate.set_x(unique_mirror.get_sb_x());
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sb_coordinate.set_y(unique_mirror.get_sb_y());
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}
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std::string sb_module_name = generate_switch_block_module_name(sb_coordinate);
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ModuleId sb_module = module_manager.find_module(sb_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
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/* Print comments */
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fp << "##################################################" << std::endl;
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fp << "# Disable timing for Switch block " << sb_module_name << std::endl;
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fp << "##################################################" << std::endl;
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/* Build a map between mux_instance name and net_num */
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std::map<std::string, int> mux_instance_to_net_map;
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/* Disable all the input/output port (routing tracks), which are not used by benchmark */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side());
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for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
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t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
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vtr::Point<size_t> port_coord(port_coordinate.get_x(), port_coordinate.get_y());
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std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type,
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port_coord, itrack,
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rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord);
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DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side());
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port_coord.set_x(unique_port_coordinate.get_x());
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port_coord.set_y(unique_port_coordinate.get_y());
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port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type,
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port_coord, itrack,
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unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
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}
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
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/* Cache the net name for routing tracks which are outputs of the switch block */
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if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
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/* Generate the name of mux instance related to this output node */
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std::string mux_instance_name = generate_sb_memory_instance_name(SWITCH_BLOCK_MUX_INSTANCE_PREFIX, side_manager.get_side(), itrack, std::string(""));
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mux_instance_to_net_map[mux_instance_name] = chan_node->vpack_net_num;
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}
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(chan_node)) {
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continue;
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}
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fp << "set_disable_timing ";
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fp << sb_instance_name << "/";
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fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
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fp << std::endl;
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}
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}
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/* Disable all the input port (grid output pins), which are not used by benchmark */
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for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
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Side side_manager(side);
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for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
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t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
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vtr::Point<size_t> port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
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rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow);
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std::string port_name = generate_grid_side_port_name(grids, port_coord,
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rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
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opin_node->ptc_num);
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if (true == compact_routing_hierarchy) {
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/* Note: use GSB coordinate when inquire for unique modules!!! */
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DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
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const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord);
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port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow);
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port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow);
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port_name = generate_grid_side_port_name(grids, port_coord,
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unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode),
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unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num);
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}
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/* Ensure we have this port in the module! */
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ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
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/* Check if this node is used by benchmark */
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if (false == is_rr_node_to_be_disable_for_analysis(opin_node)) {
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continue;
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}
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fp << "set_disable_timing ";
|
||||||
|
fp << sb_instance_name << "/";
|
||||||
|
fp << generate_sdc_port(module_manager.module_port(sb_module, module_port));
|
||||||
|
fp << std::endl;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Disable all the unused inputs of routing multiplexers, which are not used by benchmark
|
||||||
|
* Here, we start from each input of the Switch Blocks, and traverse forward to the sink
|
||||||
|
* port of the module net whose source is the input
|
||||||
|
* We will find the instance name which is the parent of the sink port, and search the
|
||||||
|
* net id through the instance_name_to_net_map
|
||||||
|
* The the net id does not match the net id of this input, we will disable the sink port!
|
||||||
|
*
|
||||||
|
* sb_module
|
||||||
|
* +-----------------------
|
||||||
|
* | MUX instance A
|
||||||
|
* | +-----------
|
||||||
|
* input_port--->|--+---x-->| sink port (disable! net_id = Y)
|
||||||
|
* (net_id = X) | | +----------
|
||||||
|
* | | MUX instance B
|
||||||
|
* | | +----------
|
||||||
|
* | +------>| sink port (do not disable! net_id = X)
|
||||||
|
*
|
||||||
|
* Because the input ports of a SB module come from
|
||||||
|
* 1. Grid output pins
|
||||||
|
* 2. routing tracks
|
||||||
|
* We will walk through these ports and do conditionally disable_timing
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Iterate over input ports coming from grid output pins */
|
||||||
|
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
|
||||||
|
Side side_manager(side);
|
||||||
|
|
||||||
|
for (size_t inode = 0; inode < rr_gsb.get_num_opin_nodes(side_manager.get_side()); ++inode) {
|
||||||
|
t_rr_node* opin_node = rr_gsb.get_opin_node(side_manager.get_side(), inode);
|
||||||
|
vtr::Point<size_t> port_coord(rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow,
|
||||||
|
rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow);
|
||||||
|
|
||||||
|
std::string port_name = generate_grid_side_port_name(grids, port_coord,
|
||||||
|
rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode),
|
||||||
|
opin_node->ptc_num);
|
||||||
|
|
||||||
|
if (true == compact_routing_hierarchy) {
|
||||||
|
/* Note: use GSB coordinate when inquire for unique modules!!! */
|
||||||
|
DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
|
||||||
|
const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord);
|
||||||
|
port_coord.set_x(unique_mirror.get_opin_node(side_manager.get_side(), inode)->xlow);
|
||||||
|
port_coord.set_y(unique_mirror.get_opin_node(side_manager.get_side(), inode)->ylow);
|
||||||
|
|
||||||
|
port_name = generate_grid_side_port_name(grids, port_coord,
|
||||||
|
unique_mirror.get_opin_node_grid_side(side_manager.get_side(), inode),
|
||||||
|
unique_mirror.get_opin_node(side_manager.get_side(), inode)->ptc_num);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Ensure we have this port in the module! */
|
||||||
|
ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
|
||||||
|
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
|
||||||
|
|
||||||
|
disable_analysis_module_input_port_net_sinks(fp, module_manager,
|
||||||
|
sb_module,
|
||||||
|
sb_instance_name,
|
||||||
|
module_port,
|
||||||
|
opin_node,
|
||||||
|
mux_instance_to_net_map);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Iterate over input ports coming from routing tracks */
|
||||||
|
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
|
||||||
|
Side side_manager(side);
|
||||||
|
DeviceCoordinator port_coordinate = rr_gsb.get_side_block_coordinator(side_manager.get_side());
|
||||||
|
|
||||||
|
for (size_t itrack = 0; itrack < rr_gsb.get_chan_width(side_manager.get_side()); ++itrack) {
|
||||||
|
/* Skip output ports, they have already been disabled or not */
|
||||||
|
if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
t_rr_node* chan_node = rr_gsb.get_chan_node(side_manager.get_side(), itrack);
|
||||||
|
|
||||||
|
vtr::Point<size_t> port_coord(port_coordinate.get_x(), port_coordinate.get_y());
|
||||||
|
std::string port_name = generate_routing_track_port_name(rr_gsb.get_chan_node(side_manager.get_side(), itrack)->type,
|
||||||
|
port_coord, itrack,
|
||||||
|
rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack));
|
||||||
|
|
||||||
|
if (true == compact_routing_hierarchy) {
|
||||||
|
/* Note: use GSB coordinate when inquire for unique modules!!! */
|
||||||
|
DeviceCoordinator sb_coord(rr_gsb.get_x(), rr_gsb.get_y());
|
||||||
|
const RRGSB& unique_mirror = L_device_rr_gsb.get_sb_unique_module(sb_coord);
|
||||||
|
DeviceCoordinator unique_port_coordinate = unique_mirror.get_side_block_coordinator(side_manager.get_side());
|
||||||
|
port_coord.set_x(unique_port_coordinate.get_x());
|
||||||
|
port_coord.set_y(unique_port_coordinate.get_y());
|
||||||
|
|
||||||
|
port_name = generate_routing_track_port_name(unique_mirror.get_chan_node(side_manager.get_side(), itrack)->type,
|
||||||
|
port_coord, itrack,
|
||||||
|
unique_mirror.get_chan_node_direction(side_manager.get_side(), itrack));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/* Ensure we have this port in the module! */
|
||||||
|
ModulePortId module_port = module_manager.find_module_port(sb_module, port_name);
|
||||||
|
VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, module_port));
|
||||||
|
|
||||||
|
disable_analysis_module_input_port_net_sinks(fp, module_manager,
|
||||||
|
sb_module,
|
||||||
|
sb_instance_name,
|
||||||
|
module_port,
|
||||||
|
chan_node,
|
||||||
|
mux_instance_to_net_map);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Iterate over all the connection blocks in a device
|
||||||
|
* and disable unused ports for each of them
|
||||||
|
*******************************************************************/
|
||||||
|
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
|
||||||
|
const std::vector<std::vector<t_grid_tile>>& grids,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const DeviceRRGSB& L_device_rr_gsb,
|
||||||
|
const bool& compact_routing_hierarchy) {
|
||||||
|
|
||||||
|
/* Build unique X-direction connection block modules */
|
||||||
|
DeviceCoordinator sb_range = L_device_rr_gsb.get_gsb_range();
|
||||||
|
|
||||||
|
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
|
||||||
|
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
|
||||||
|
/* Check if the connection block exists in the device!
|
||||||
|
* Some of them do NOT exist due to heterogeneous blocks (height > 1)
|
||||||
|
* We will skip those modules
|
||||||
|
*/
|
||||||
|
const RRGSB& rr_gsb = L_device_rr_gsb.get_gsb(ix, iy);
|
||||||
|
|
||||||
|
print_analysis_sdc_disable_sb_unused_resources(fp, grids,
|
||||||
|
module_manager,
|
||||||
|
L_device_rr_gsb,
|
||||||
|
rr_gsb,
|
||||||
|
compact_routing_hierarchy);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -12,4 +12,11 @@ void print_analysis_sdc_disable_unused_cbs(std::fstream& fp,
|
||||||
const ModuleManager& module_manager,
|
const ModuleManager& module_manager,
|
||||||
const DeviceRRGSB& L_device_rr_gsb,
|
const DeviceRRGSB& L_device_rr_gsb,
|
||||||
const bool& compact_routing_hierarchy);
|
const bool& compact_routing_hierarchy);
|
||||||
|
|
||||||
|
void print_analysis_sdc_disable_unused_sbs(std::fstream& fp,
|
||||||
|
const std::vector<std::vector<t_grid_tile>>& grids,
|
||||||
|
const ModuleManager& module_manager,
|
||||||
|
const DeviceRRGSB& L_device_rr_gsb,
|
||||||
|
const bool& compact_routing_hierarchy);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
|
||||||
|
|
@ -242,22 +242,17 @@ void print_analysis_sdc(const std::string& sdc_dir,
|
||||||
format_dir_path(module_manager.module_name(top_module)));
|
format_dir_path(module_manager.module_name(top_module)));
|
||||||
|
|
||||||
|
|
||||||
/* TODO: Disable timing for unused routing resources in connection blocks */
|
/* Disable timing for unused routing resources in connection blocks */
|
||||||
print_analysis_sdc_disable_unused_cbs(fp, L_grids,
|
print_analysis_sdc_disable_unused_cbs(fp, L_grids,
|
||||||
module_manager,
|
module_manager,
|
||||||
L_device_rr_gsb,
|
L_device_rr_gsb,
|
||||||
compact_routing_hierarchy);
|
compact_routing_hierarchy);
|
||||||
|
|
||||||
/* TODO: Disable timing for unused routing resources in switch blocks */
|
/* Disable timing for unused routing resources in switch blocks */
|
||||||
/*
|
print_analysis_sdc_disable_unused_sbs(fp, L_grids,
|
||||||
if (TRUE == compact_routing_hierarchy) {
|
module_manager,
|
||||||
verilog_generate_sdc_disable_unused_sbs(fp);
|
L_device_rr_gsb,
|
||||||
verilog_generate_sdc_disable_unused_sbs_muxs(fp);
|
compact_routing_hierarchy);
|
||||||
} else {
|
|
||||||
verilog_generate_sdc_disable_unused_sbs(fp, LL_nx, LL_ny);
|
|
||||||
verilog_generate_sdc_disable_unused_sbs_muxs(fp, LL_nx, LL_ny);
|
|
||||||
}
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* TODO: Disable timing for unused routing resources in grids (programmable blocks) */
|
/* TODO: Disable timing for unused routing resources in grids (programmable blocks) */
|
||||||
/*
|
/*
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue