diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst index ac57bb1cc..0cd489293 100644 --- a/docs/source/manual/file_formats/index.rst +++ b/docs/source/manual/file_formats/index.rst @@ -38,4 +38,4 @@ OpenFPGA widely uses XML format for interchangable files io_naming_file - tile_config_tile + tile_config_file diff --git a/docs/source/manual/fpga_verilog/fabric_netlist.rst b/docs/source/manual/fpga_verilog/fabric_netlist.rst index f09575a84..17b64115e 100644 --- a/docs/source/manual/fpga_verilog/fabric_netlist.rst +++ b/docs/source/manual/fpga_verilog/fabric_netlist.rst @@ -5,9 +5,9 @@ Fabric Netlists In this part, we will introduce the hierarchy, dependency and functionality of each Verilog netlist, which are generated to model the FPGA fabric. -.. note:: These netlists are automatically generated by the OpenFPGA command ``write_fabric_verilog``. See :ref:`openfpga_verilog_commands` for its detailed usage. +.. note:: These netlists are automatically generated by the OpenFPGA command :ref:`cmd_write_fabric_verilog`. See :ref:`openfpga_verilog_commands` for its detailed usage. -All the generated Verilog netlists are located in the directory as you specify in the OpenFPGA command ``write_fabric_verilog``. +All the generated Verilog netlists are located in the directory as you specify in the OpenFPGA command :ref:`cmd_write_fabric_verilog`. Inside the directory, the Verilog netlists are organized as illustrated in :numref:`fig_fabric_netlist_hierarchy`. .. _fig_fabric_netlist_hierarchy: @@ -24,6 +24,8 @@ Inside the directory, the Verilog netlists are organized as illustrated in :numr An illustrative FPGA fabric modelled by the Verilog netlists +.. _fabric_netlists_top_level_netlists: + Top-level Netlists ~~~~~~~~~~~~~~~~~~ @@ -48,6 +50,21 @@ Top-level Netlists .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly. +.. _fabric_netlists_tiles: + +Tiles +~~~~~ + +This sub-directory contains all the tile-level modules. Only seen when the ``--group_tile`` option is enabled when calling command :ref:`cmd_build_fabric`. +Each tile groups a number of programmable blocks (:ref:`fabric_netlists_logic_blocks`) and routing blocks (:ref:`fabric_netlists_routing_blocks`), as depicted in :numref:`fig_generic_fabric`. +Tiles are instanciated under the top-level module (:ref:`fabric_netlists_top_level_netlists`). + +.. option:: tile____.v + + For each unique tile, a Verilog netlist will be generated. The ```` and ```` denote the coordinate of the tile in the FPGA fabric. + +.. _fabric_netlists_logic_blocks: + Logic Blocks ~~~~~~~~~~~~ This sub-directory contains all the Verilog modules modeling configurable logic blocks, heterogeneous blocks as well as I/O blocks. @@ -63,6 +80,8 @@ Take the example in :numref:`fig_generic_fabric`, the modules are CLBs, DSP bloc For each root ``pb_type`` defined in the ```` of VPR architecture description, a Verilog netlist will be generated to model its internal structure. +.. _fabric_netlists_routing_blocks: + Routing Blocks ~~~~~~~~~~~~~~ This sub-directory contains all the Verilog modules modeling Switch Blocks (SBs) and Connection Blocks (CBs). diff --git a/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png b/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png index 232eb940c..27811bfb7 100644 Binary files a/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png and b/docs/source/manual/fpga_verilog/figures/fabric_netlist_hierarchy.png differ diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index d29c4c172..a21c4dbfe 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -3,6 +3,8 @@ FPGA-Verilog ------------ +.. _cmd_write_fabric_verilog: + write_fabric_verilog ~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst index add629dc6..7aaa2f7e6 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst @@ -255,7 +255,7 @@ build_fabric .. option:: --group_tile - Group fine-grained programmable blocks, connection blocks and switch blocks into tiles. Once enabled, tiles will be added to the top-level module. Otherwise, the top-level module consists of programmable blocks, connection blocks and switch blocks. The tile style can be customized through a file. See details in :ref:`file_formats_tile_config_file`. + Group fine-grained programmable blocks, connection blocks and switch blocks into tiles. Once enabled, tiles will be added to the top-level module. Otherwise, the top-level module consists of programmable blocks, connection blocks and switch blocks. The tile style can be customized through a file. See details in :ref:`file_formats_tile_config_file`. When enabled, the Verilog netlists will contain additional netlists that model tiles (see details in :ref:`fabric_netlists_tiles`). .. warning:: This option does not support ``--duplicate_grid_pin``!