diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml b/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
index f056d3b9b..9ee90ce4b 100644
--- a/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
+++ b/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
@@ -174,7 +174,7 @@
         </input>
       </stimulate>      
     </parameters>
-    <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="OPENFPGAPATH/vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
+    <tech_lib lib_type="academia" transistor_type="TOP_TT" lib_path="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/tech/PTM_45nm/45nm.pm" nominal_vdd="1.0" io_vdd="2.5"/>
     <transistors pn_ratio="2" model_ref="M">
       <nmos model_name="nmos" chan_length="45e-9" min_width="140e-9"/>
       <pmos model_name="pmos" chan_length="45e-9" min_width="140e-9"/>
@@ -278,7 +278,7 @@
         <port type="sram" prefix="sram" size="1"/>
       </circuit_model>
       <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/ff.v">
+      <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
          <input_buffer exist="on" circuit_model_name="INVTX1"/>
          <output_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -299,7 +299,7 @@
         <port type="output" prefix="out" size="1"/>
         <port type="sram" prefix="sram" size="64"/>
       </circuit_model>
-      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v" >
+      <circuit_model type="sram" name="sram6T" prefix="sram" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/VerilogNetlists/sram.v" >
         <design_technology type="cmos"/>
         <input_buffer exist="on" circuit_model_name="INVTX1"/>
         <output_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -307,7 +307,7 @@
         <port type="input" prefix="in" size="1"/>
         <port type="output" prefix="out" size="2"/>
       </circuit_model>
-      <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/sram.v">
+      <circuit_model type="sram" name="sram6T_blwl" prefix="sram_blwl" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/SpiceNetlists/sram.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/VerilogNetlists/sram.v">
 
         <design_technology type="cmos"/>
         <input_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -320,7 +320,7 @@
         <port type="wl" prefix="wl" size="1" default_val="0" inv_circuit_model_name="INVTX1"/>
       </circuit_model>
       <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-      <circuit_model type="sff" name="sc_dff" prefix="scff" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/ff.v">
+      <circuit_model type="sff" name="sc_dff" prefix="scff" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/SpiceNetlists/ff.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/VerilogNetlists/ff.v">
          <design_technology type="cmos"/>
          <input_buffer exist="on" circuit_model_name="INVTX1"/>
          <output_buffer exist="on" circuit_model_name="INVTX1"/>
@@ -331,7 +331,7 @@
          <port type="output" prefix="Q" size="2"/>
          <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true" is_prog="true"/>
       </circuit_model>
-      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="OPENFPGAPATH/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="OPENFPGAPATH/vpr7_x2p/vpr/VerilogNetlists/io.v">
+      <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/tang/research/EDA/OpenFPGA/vpr7_x2p/vpr/../../vpr7_x2p/vpr/VerilogNetlists/io.v">
         <design_technology type="cmos"/>
         <input_buffer exist="on" circuit_model_name="INVTX1"/>
         <output_buffer exist="on" circuit_model_name="INVTX1"/>
diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_mux.c b/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_mux.c
index 76edce0d0..daac233b4 100644
--- a/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_mux.c
+++ b/vpr7_x2p/vpr/SRC/fpga_spice/spice/spice_mux.c
@@ -796,10 +796,9 @@ void fprint_spice_mux_model_cmos_subckt(FILE* fp,
   fprintf(fp, "\n");
 
   /* Handle the corner case: input size = 2  */
-  if (2 == mux_size) {
+  cur_mux_structure = spice_model.design_tech_info.structure;
+  if (2 == spice_mux_arch.num_input) {
     cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL;
-  } else {
-    cur_mux_structure = spice_model.design_tech_info.structure;
   }
   
   /* Print internal architecture*/ 
diff --git a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c
index b8afaada1..38198c4eb 100644
--- a/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c
+++ b/vpr7_x2p/vpr/SRC/fpga_spice/verilog/verilog_submodules.c
@@ -1179,6 +1179,8 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
   t_spice_model_port** output_port = NULL;
   t_spice_model_port** sram_port = NULL;
 
+  enum e_spice_model_structure cur_mux_structure;
+
   /* Find the basis subckt*/
   char* mux_basis_subckt_name = NULL;
   char* mux_special_basis_subckt_name = NULL;
@@ -1261,9 +1263,15 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
   /* Print local vdd and gnd*/
   fprintf(fp, ");");
   fprintf(fp, "\n");
+
+  /* Handle the corner case: input size = 2  */
+  cur_mux_structure = spice_model.design_tech_info.structure;
+  if (2 == spice_mux_arch.num_input) {
+    cur_mux_structure = SPICE_MODEL_STRUCTURE_ONELEVEL;
+  }
   
   /* Print internal architecture*/ 
-  switch (spice_model.design_tech_info.structure) {
+  switch (cur_mux_structure) {
   case SPICE_MODEL_STRUCTURE_TREE:
     dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, 
                                          spice_model, spice_mux_arch, num_sram_port, sram_port);