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[core] typo

This commit is contained in:
tangxifan 2024-06-29 17:17:54 -07:00
parent bc2f02866d
commit 5dd0549aed
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/tasks/basic_tests/clock_network/homo_2clock_2layer/config/clk_arch_2clk_2layer.xml
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@ -11,8 +11,8 @@
<spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/> <spine name="rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/> <spine name="rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps> <taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:1]"/> <all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[1:1]" to_pin="clb[0:0].clk[0:1]"/> <all from_pin="clk[1:1]" to_pin="clb[0:0].clk[0:0]"/>
</taps> </taps>
</clock_network> </clock_network>
</clock_networks> </clock_networks>