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BaudouinChauviere 2019-01-03 18:26:30 +01:00 committed by GitHub
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docs/source/index.rst
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@ -41,7 +41,7 @@ Welcome to OpenFPGA's documentation!
contact contact
reference reference
For more information on the VTR see [vtr_doc](https://docs.verilogtorouting.org/en/latest/) // [vtr_github](https://github.com/verilog-to-routing/vtr-verilog-to-routing) For more information on the VTR see vtr_doc_ // vtr_github_
For more information on the Yosys see yosys_doc_ // yosys_github_ For more information on the Yosys see yosys_doc_ // yosys_github_
@ -56,8 +56,8 @@ Indices and tables
* :ref:`modindex` * :ref:`modindex`
* :ref:`search` * :ref:`search`
.. _vpr_doc: https://docs.verilogtorouting.org/en/latest/ .. _vtr_doc: https://docs.verilogtorouting.org/en/latest/
.. _vpr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing .. _vtr_github: https://github.com/verilog-to-routing/vtr-verilog-to-routing
.. _yosys_doc: http://www.clifford.at/yosys/ .. _yosys_doc: http://www.clifford.at/yosys/
.. _yosys_github: https://github.com/YosysHQ/yosys .. _yosys_github: https://github.com/YosysHQ/yosys
.. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/ .. _xml_vtr: https://docs.verilogtorouting.org/en/latest/arch/reference/