diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index 138ee2032..c32e9ae87 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -38,7 +38,7 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_read_file = cmd.option("read_file");
 
   if (true == cmd_context.option_enable(cmd, opt_read_file)) {
-    openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(cmd_context.option_value(cmd, opt_write_file).c_str());
+    openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(cmd_context.option_value(cmd, opt_read_file).c_str());
   } else {
     openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx,
                                                                       openfpga_ctx,
diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif b/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
new file mode 100644
index 000000000..fc79555cb
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
@@ -0,0 +1,12 @@
+# This BLIF is created to test the feature of
+# loading external bitstream files.
+# Therefore, its module name is and2 rather than or2
+# Please do NOT use this file is regular regression tests
+.model and2
+.inputs a b
+.outputs c
+
+.names a b c
+00 0
+
+.end
diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index 2d7eb177f..d36f074ae 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -25,10 +25,12 @@ openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_b
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = or2
+# We use a special BLIF file whose top module name is and2
+# in order to be consistent with the architecture bistream design name
+bench0_top = and2
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
 ########################
 # Use a different verilog as reference here