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refine doc hierarchy

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tangxifan 2018-09-14 13:27:05 -06:00
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docs/source/arch_lang/circuit_modules.rst
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Define Circuit-level Modules Define Circuit-level Modules
======================================================================== ----------------------------
To support FPGA SPICE, Verilog and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks. To support FPGA SPICE, Verilog and Bitstream Generator, physical modules containing gate-level and transistor-level features are required for FPGA primitive blocks.
The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language. The physical modules are defined in XML syntax, similar to the original VPR FPGA architecture description language.

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docs/source/arch_lang/link_circuit_modules.rst
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Link circuit modules Link circuit modules
==================== --------------------
Each defined SPICE model should be linked to a FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to SPICE models. Each defined SPICE model should be linked to a FPGA module defined in the original part of architecture descriptions. It helps FPGA-SPICE creating the SPICE netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to SPICE models.
SRAM SRAM