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OpenFPGA
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reshape bram test case

This commit is contained in:
tangxifan 2020-04-12 14:32:09 -06:00
parent 600a48edc7
commit 5d665aa04b
2 changed files with 1 additions and 1 deletions
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.travis/script.sh
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@ -58,6 +58,6 @@ echo -e "Testing Verilog generation with hard adder chain in CLBs ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/hard_adder --debug --show_thread_logs
echo -e "Testing Verilog generation with 16k block RAMs "; echo -e "Testing Verilog generation with 16k block RAMs ";
python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/bram/dpram16k --debug --show_thread_logs
end_section "OpenFPGA.TaskTun" end_section "OpenFPGA.TaskTun"

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openfpga_flow/tasks/openfpga_shell/bram/config/task.conf → openfpga_flow/tasks/openfpga_shell/bram/dpram16k/config/task.conf
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