From 5d60b4ef8c27b7088008d7e596354a25ca1e6a95 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 23:02:49 -0600 Subject: [PATCH] [Architecture] Add openfpga architecture and Verilog HDL for configurable latch with active-low set --- .../VerilogNetlists/config_latch_neg_set.v | 37 ++++ .../k4_N4_40nm_frame_use_setb_openfpga.xml | 199 ++++++++++++++++++ 2 files changed, 236 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/config_latch_neg_set.v create mode 100644 openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml diff --git a/openfpga_flow/VerilogNetlists/config_latch_neg_set.v b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v new file mode 100644 index 000000000..2c23a73d1 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/config_latch_neg_set.v @@ -0,0 +1,37 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Function : A Configurable Latch where data storage +// can be updated when wl is enabled +// Reset is active low +// Coder : Xifan TANG +//----------------------------------------------------- +module config_latch_neg_set ( + input setb, // Reset input + input wl, // Data Enable + input bl, // Data Input + output Q, // Q output + output Qb // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (setb or wl or bl) begin + if (~setb) begin + q_reg <= 1'b1; + end else if (1'b1 == wl) begin + q_reg <= bl; + end +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q +assign Q = q_reg; +assign Qb = ~q_reg; +`else +assign Q = 1'bZ; +assign Qb = !Q; +`endif + +endmodule diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml new file mode 100644 index 000000000..670339321 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +