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[Script] Allow users to specify custom post-synthesis verilog for simulation

This commit is contained in:
tangxifan 2021-03-10 11:45:55 -07:00
parent aafd87c3f9
commit 5d46537b5b
1 changed files with 7 additions and 6 deletions
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1
openfpga_flow/scripts/run_fpga_task.py
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@ -279,6 +279,7 @@ def generate_each_task_actions(taskname):
"for vpr_blif flow") "for vpr_blif flow")
CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act") CurrBenchPara["activity_file"] = SynthSection.get(bech_name+"_act")
# Allow user to specify a post-synthesis verilog file for simulation usage
# Check if base verilog file exists # Check if base verilog file exists
if not SynthSection.get(bech_name+"_verilog"): if not SynthSection.get(bech_name+"_verilog"):
clean_up_and_exit("Missing argument %s for vpr_blif flow" % clean_up_and_exit("Missing argument %s for vpr_blif flow" %