From 5d0b0b9a8cbc8e32a50ccd064296805b11d69191 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 26 Jun 2024 22:46:12 -0700 Subject: [PATCH] [core] now global nets mapping are applied to clock routing --- .../annotation/openfpga_annotate_routing.cpp | 44 +++++++++++++++++++ .../annotation/openfpga_annotate_routing.h | 6 +++ .../src/annotation/route_clock_rr_graph.cpp | 29 +++++++----- .../src/annotation/route_clock_rr_graph.h | 1 + .../src/base/openfpga_link_arch_template.h | 1 + 5 files changed, 69 insertions(+), 12 deletions(-) diff --git a/openfpga/src/annotation/openfpga_annotate_routing.cpp b/openfpga/src/annotation/openfpga_annotate_routing.cpp index 780b1d99d..8c19cd2c7 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.cpp +++ b/openfpga/src/annotation/openfpga_annotate_routing.cpp @@ -8,10 +8,54 @@ #include "old_traceback.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vtr_time.h" /* begin namespace openfpga */ namespace openfpga { +/******************************************************************** + * Create a mapping between each rr_node and its mapped nets + * - Only applicable to global nets for dedicated clock routing purpose + * - Note that this function is different than annotate_vpr_rr_nodes() + * Please do not annotate global nets in vpr_routing_annotation! + *******************************************************************/ +vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, + const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const bool& verbose) { + vtr::vector rr_node_nets; + + size_t counter = 0; + vtr::ScopedStartFinishTimer timer("Annotating rr_node with global nets"); + + const auto& rr_graph = device_ctx.rr_graph; + + rr_node_nets.resize(rr_graph.num_nodes(), ClusterNetId::INVALID()); + + size_t layer = 0; + + for (ClusterNetId net_id : cluster_nlist.nets()) { + if (!cluster_nlist.net_is_ignored(net_id)) { + continue; + } + /* Walk through all the sinks */ + for (ClusterPinId pin_id : cluster_nlist.net_pins(net_id)) { + ClusterBlockId block_id = cluster_nlist.pin_block(pin_id); + t_block_loc blk_loc = get_block_loc(block_id, false); + int phy_pin = placement_ctx.physical_pins[pin_id]; + std::vector curr_rr_nodes = rr_graph.node_lookup().find_nodes_at_all_sides(layer, blk_loc.loc.x, blk_loc.loc.y, IPIN, phy_pin); + for (RRNodeId curr_rr_node : curr_rr_nodes) { + rr_node_nets[curr_rr_node] = net_id; + } + } + } + + VTR_LOGV(verbose, "Done with %d nodes mapping\n", counter); + + + return rr_node_nets; +} + /******************************************************************** * Create a mapping between each rr_node and its mapped nets * based on VPR routing results diff --git a/openfpga/src/annotation/openfpga_annotate_routing.h b/openfpga/src/annotation/openfpga_annotate_routing.h index aa79e69d5..2578e86bd 100644 --- a/openfpga/src/annotation/openfpga_annotate_routing.h +++ b/openfpga/src/annotation/openfpga_annotate_routing.h @@ -15,6 +15,12 @@ /* begin namespace openfpga */ namespace openfpga { +vtr::vector annotate_rr_node_global_net(const DeviceContext& device_ctx, + const ClusteredNetlist& cluster_nlist, + const PlacementContext& placement_ctx, + const bool& verbose); + + void annotate_vpr_rr_node_nets(const DeviceContext& device_ctx, const ClusteringContext& clustering_ctx, const RoutingContext& routing_ctx, diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index 01a7dbf1c..77de0175b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -6,6 +6,7 @@ #include "vtr_geometry.h" #include "vtr_log.h" #include "vtr_time.h" +#include "openfpga_annotate_routing.h" /* begin namespace openfpga */ namespace openfpga { @@ -87,6 +88,7 @@ static int build_clock_tree_net_map( static int route_clock_tree_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, const RRGraphView& rr_graph, const RRClockSpatialLookup& clk_rr_lookup, + const vtr::vector& rr_node_gnets, const std::map& tree2clk_pin_map, const ClockNetwork& clk_ntwk, const ClockTreeId& clk_tree, const bool& verbose) { @@ -179,17 +181,16 @@ static int route_clock_tree_rr_graph( clk_ntwk.spine_name(ispine).c_str()); continue; } - //if (!vpr_routing_annotation.rr_node_net(des_node)) { - // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", - // clk_ntwk.spine_name(ispine).c_str()); - // continue; - //} - //if (vpr_routing_annotation.rr_node_net(des_node) != - // tree2clk_pin_map.at(ipin)) { - // VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", - // clk_ntwk.spine_name(ispine).c_str()); - // continue; - //} + if (!rr_node_gnets[des_node]) { + VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the IPIN is not mapped\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } + if (rr_node_gnets[des_node] != tree2clk_pin_map.at(ipin)) { + VTR_LOGV(verbose, "Skip routing clock tap of spine '%s' as the net mapping does not match clock net\n", + clk_ntwk.spine_name(ispine).c_str()); + continue; + } VTR_ASSERT(rr_graph.valid_node(src_node)); VTR_ASSERT(rr_graph.valid_node(des_node)); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, @@ -219,6 +220,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, @@ -253,6 +255,9 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, return CMD_EXEC_FATAL_ERROR; } + /* Build rr_node-to-net mapping for global nets */ + vtr::vector rr_node_gnets = annotate_rr_node_global_net(vpr_device_ctx, cluster_nlist, vpr_place_ctx, verbose); + /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { VTR_LOGV(verbose, "Build clock name to clock tree '%s' pin mapping...\n", @@ -269,7 +274,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, VTR_LOGV(verbose, "Routing clock tree '%s'...\n", clk_ntwk.tree_name(itree).c_str()); status = route_clock_tree_rr_graph( - vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, + vpr_routing_annotation, vpr_device_ctx.rr_graph, clk_rr_lookup, rr_node_gnets, tree2clk_pin_map, clk_ntwk, itree, verbose); if (status == CMD_EXEC_FATAL_ERROR) { return status; diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 6a1b2cad4..e12767e9b 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -22,6 +22,7 @@ int route_clock_rr_graph(VprRoutingAnnotation& vpr_routing_annotation, const DeviceContext& vpr_device_ctx, const AtomContext& atom_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const VprNetlistAnnotation& netlist_annotation, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index cb16de224..319c89086 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -231,6 +231,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), g_vpr_ctx.atom(), g_vpr_ctx.clustering().clb_nlist, + g_vpr_ctx.placement(), openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_verbose));