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sample_arch:move cmos/rram variation to technology library XML nodes

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tangxifan 2020-01-16 20:58:45 -07:00
parent 95edd3c091
commit 5c69f57559
1 changed files with 8 additions and 6 deletions
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14
libopenfpga/libarchopenfpga/arch/sample_arch.xml
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@ -13,13 +13,18 @@
<logic_transistors pn_ratio="2" model_ref="M" vdd="0.9"> <logic_transistors pn_ratio="2" model_ref="M" vdd="0.9">
<nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/> <nmos model_name="nch" chan_length="40e-9" min_width="140e-9"/>
<pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/> <pmos model_name="pch" chan_length="40e-9" min_width="140e-9"/>
<variation abs_variation="0.1" num_sigma="3"/>
</logic_transistors> </logic_transistors>
<io_transistors pn_ratio="2" model_ref="M" vdd="2.5"> <io_transistors pn_ratio="2" model_ref="M" vdd="2.5">
<nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/> <nmos model_name="nch_25" chan_length="270e-9" min_width="320e-9"/>
<pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/> <pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
</io_transistors> </io_transistors>
<rram model_name="rram_mem" rlrs="1e4" rhrs="1e5"/> <rram model_name="rram_mem" rlrs="1e4" rhrs="1e5">
<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6"/> <variation abs_variation="0.1" num_sigma="3"/>
</rram>
<rram model_name="rram_logic" rlrs="5e3" rhrs="20e6">
<variation abs_variation="0.1" num_sigma="3"/>
</rram>
</technology> </technology>
<circuit_library> <circuit_library>
<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true"> <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
@ -239,10 +244,7 @@
</openfpga_architecture> </openfpga_architecture>
<openfpga_simulation_setting> <openfpga_simulation_setting>
<general sim_temp="25" post="false" captab="false" fast="true"/> <general sim_temp="25" post="false" captab="false" fast="true"/>
<monte_carlo mc_sim="false" num_mc_points="2" cmos_variation="false" rram_variation="false"> <monte_carlo mc_sim="false" num_mc_points="2"/>
<cmos abs_variation="0.1" num_sigma="3"/>
<rram abs_variation="0.1" num_sigma="3"/>
</monte_carlo>
<measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs"> <measure sim_num_clock_cycle="auto" accuracy="1e-13" accuracy_type="abs">
<slew> <slew>
<rise upper_thres_pct="0.95" lower_thres_pct="0.05"/> <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>