[HDL] Updated cell library with the SRAM cell with Read Enable signal
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openfpga_flow/openfpga_cell_library/verilog
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@ -256,6 +256,44 @@ module SRAMSR(
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endmodule
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endmodule
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//-----------------------------------------------------
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// Function : A SRAM cell with WL read signal
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//-----------------------------------------------------
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module SRAM_RE(
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input WE, // Word line control signal as write enable
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input RE, // Word line read signal as read enable
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inout D, // Bit line control signal
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output Q, // Data output
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output QN // Data output
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);
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//----- local variable need to be registered
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reg data;
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reg data_readback;
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//----- when wl is enabled, we can read in data from bl
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always @(WE or RE or D)
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begin
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if (1'b1 == RE) begin
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data_readback <= Q;
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end else if ((1'b1 == D)&&(1'b1 == WE)) begin
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//----- Cases to program internal memory bit
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//----- case 1: bl = 1, wl = 1, a -> 0
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data <= 1'b1;
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end else if ((1'b0 == D)&&(1'b1 == WE)) begin
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//----- case 2: bl = 0, wl = 1, a -> 0
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data <= 1'b0;
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end
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end
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// Wire q_reg to Q
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assign Q = data;
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assign QN = ~data;
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assign D = RE ? data_readback : 1'b0;
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endmodule
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//-----------------------------------------------------
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//-----------------------------------------------------
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// Function : A SRAM cell with
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// Function : A SRAM cell with
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// - an active-low reset
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// - an active-low reset
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