tileable rr_graph builder ready to debug

libs/libarchfpga/src/physical_types.h

@@ -1590,12 +1590,16 @@ struct t_clock_arch_spec {
 struct t_arch {
     char* architecture_id; //Secure hash digest of the architecture file to uniquely identify this architecture
     
+    bool tileable;
+
     t_chan_width_dist Chans;
     enum e_switch_block_type SBType;
+    enum e_switch_block_type SBSubType;
     std::vector<t_switchblock_inf> switchblocks;
     float R_minW_nmos;
     float R_minW_pmos;
     int Fs;
+    int subFs;
     float grid_logic_tile_area;
     std::vector<t_segment_inf> Segments;
     t_arch_switch_inf* Switches = nullptr;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2533,8 +2533,10 @@ static void ProcessModelPorts(pugi::xml_node port_group, t_model* model, std::se
 static void ProcessLayout(pugi::xml_node layout_tag, t_arch* arch, const pugiutil::loc_data& loc_data) {
     VTR_ASSERT(layout_tag.name() == std::string("layout"));
 
-    //Expect no attributes on <layout>
+    //Expect only tileable attributes on <layout>
-    expect_only_attributes(layout_tag, {}, loc_data);
+    //expect_only_attributes(layout_tag, {"tileable"}, loc_data);
+
+    arch->tileable = get_attribute(layout_tag, "tileable", loc_data).as_bool();
 
     //Count the number of <auto_layout> or <fixed_layout> tags
     size_t auto_layout_cnt = 0;
@@ -2882,7 +2884,7 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
 
     //<switch_block> tag
     Cur = get_single_child(Node, "switch_block", loc_data);
-    expect_only_attributes(Cur, {"type", "fs"}, loc_data);
+    //expect_only_attributes(Cur, {"type", "fs", "sub_type", "sub_fs"}, loc_data);
     Prop = get_attribute(Cur, "type", loc_data).value();
     if (strcmp(Prop, "wilton") == 0) {
         arch->SBType = WILTON;
@@ -2898,8 +2900,21 @@ static void ProcessDevice(pugi::xml_node Node, t_arch* arch, t_default_fc_spec&
                        "Unknown property %s for switch block type x\n", Prop);
     }
 
+    Prop = get_attribute(Cur, "sub_type", loc_data, BoolToReqOpt(false)).value();
+    if (strcmp(Prop, "wilton") == 0) {
+        arch->SBSubType = WILTON;
+    } else if (strcmp(Prop, "universal") == 0) {
+        arch->SBSubType = UNIVERSAL;
+    } else if (strcmp(Prop, "subset") == 0) {
+        arch->SBSubType = SUBSET;
+    } else {
+        archfpga_throw(loc_data.filename_c_str(), loc_data.line(Cur),
+                       "Unknown property %s for switch block subtype x\n", Prop);
+    }
+
     ReqOpt CUSTOM_SWITCHBLOCK_REQD = BoolToReqOpt(!custom_switch_block);
     arch->Fs = get_attribute(Cur, "fs", loc_data, CUSTOM_SWITCHBLOCK_REQD).as_int(3);
+    arch->subFs = get_attribute(Cur, "sub_fs", loc_data,  BoolToReqOpt(false)).as_int(3);
 
     Cur = get_single_child(Node, "default_fc", loc_data, ReqOpt::OPTIONAL);
     if (Cur) {

openfpga/test_vpr_arch/k6_frac_N10_40nm.xml

@@ -76,7 +76,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout>
+  <layout tileable="true">
     <auto_layout aspect_ratio="1.0">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -110,7 +110,7 @@
       <x distr="uniform" peak="1.000000"/>
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
     <connection_block input_switch_name="ipin_cblock"/>
   </device>
   <switchlist>

vpr/src/base/SetupVPR.cpp

@@ -309,9 +309,11 @@ static void SetupSwitches(const t_arch& Arch,
 static void SetupRoutingArch(const t_arch& Arch,
                              t_det_routing_arch* RoutingArch) {
     RoutingArch->switch_block_type = Arch.SBType;
+    RoutingArch->switch_block_subtype = Arch.SBSubType;
     RoutingArch->R_minW_nmos = Arch.R_minW_nmos;
     RoutingArch->R_minW_pmos = Arch.R_minW_pmos;
     RoutingArch->Fs = Arch.Fs;
+    RoutingArch->subFs = Arch.subFs;
     RoutingArch->directionality = BI_DIRECTIONAL;
     if (Arch.Segments.size()) {
         RoutingArch->directionality = Arch.Segments[0].directionality;