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[core] fixed multiple bugs on fabric generator on supporting group_config_block

This commit is contained in:
tangxifan 2023-08-04 12:36:59 -07:00
parent 3c2518ac70
commit 5bc8925c3a
6 changed files with 44 additions and 19 deletions
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20
openfpga/src/fabric/build_grid_modules.cpp
View File

@ -278,7 +278,7 @@ static void build_primitive_block_module(
std::string primitive_module_name =
generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
VTR_LOGV(verbose, "Building primitive module '%s'...",
VTR_LOGV(verbose, "Building primitive module '%s'...\n",
primitive_module_name.c_str());
/* Create a module of the primitive LUT and register it to module manager */
@ -372,6 +372,11 @@ static void build_primitive_block_module(
std::string(MEMORY_MODULE_POSTFIX), false);
ModuleId physical_memory_module =
module_manager.find_module(physical_memory_module_name);
VTR_LOGV(verbose,
"Mapping feedthrough memory module '%s' to physical memory "
"module '%s'...\n",
memory_module_name.c_str(), physical_memory_module_name.c_str());
VTR_ASSERT(module_manager.valid_module_id(physical_memory_module));
module_manager.set_logical2physical_configurable_child(
primitive_module, config_child_id, physical_memory_module);
}
@ -384,7 +389,7 @@ static void build_primitive_block_module(
if (0 < module_manager.num_configurable_children(
primitive_module, ModuleManager::e_config_child_type::LOGICAL)) {
add_module_nets_memory_config_bus(
module_manager, decoder_lib, primitive_module, sram_orgz_type,
module_manager, decoder_lib, primitive_module, mem_module_type,
circuit_lib.design_tech_type(sram_model),
ModuleManager::e_config_child_type::LOGICAL);
}
@ -680,7 +685,11 @@ static void add_module_pb_graph_pin_interc(
std::string(MEMORY_MODULE_POSTFIX));
ModuleId phy_mem_module =
module_manager.find_module(phy_mem_module_name);
VTR_ASSERT(true == module_manager.valid_module_id(phy_mem_module));
VTR_ASSERT(module_manager.valid_module_id(phy_mem_module));
VTR_LOGV(verbose,
"Mapping feedthrough memory module '%s' to physical memory "
"module '%s'...\n",
mux_mem_module_name.c_str(), phy_mem_module_name.c_str());
module_manager.set_logical2physical_configurable_child(
pb_module, config_child_id, phy_mem_module);
VTR_LOGV(verbose, "Now use a feedthrough memory for '%s'\n",
@ -978,7 +987,7 @@ static void rec_build_logical_tile_modules(
std::string pb_module_name =
generate_physical_block_module_name(physical_pb_type);
VTR_LOGV(verbose, "Building module '%s'...", pb_module_name.c_str());
VTR_LOGV(verbose, "Building module '%s'...\n", pb_module_name.c_str());
/* Register the Verilog module in module manager */
ModuleId pb_module = module_manager.add_module(pb_module_name);
@ -1201,7 +1210,8 @@ static void build_physical_tile_module(
/* TODO: Add a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, grid_module,
circuit_lib, sram_orgz_type, sram_model);
circuit_lib, sram_orgz_type, sram_model,
verbose);
}
/* Add grid ports(pins) to the module */

20
openfpga/src/fabric/build_memory_modules.cpp
View File

@ -1243,9 +1243,9 @@ int build_memory_modules(ModuleManager& module_manager,
verbose);
/* Create feedthrough memory module */
if (require_feedthrough_memory) {
module_name = generate_memory_module_name(
circuit_lib, model, sram_models[0],
std::string(MEMORY_FEEDTHROUGH_MODULE_POSTFIX));
module_name =
generate_memory_module_name(circuit_lib, model, sram_models[0],
std::string(MEMORY_MODULE_POSTFIX), true);
status = build_feedthrough_memory_module(module_manager, module_name,
num_mems, verbose);
if (status != CMD_EXEC_SUCCESS) {
@ -1310,7 +1310,9 @@ int build_memory_group_module(ModuleManager& module_manager,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const size_t& num_mems) {
const size_t& num_mems, const bool& verbose) {
VTR_LOGV(verbose, "Building memory group module '%s'...\n",
module_name.c_str());
ModuleId mem_module = module_manager.add_module(module_name);
if (!module_manager.valid_module_id(mem_module)) {
return CMD_EXEC_FATAL_ERROR;
@ -1442,13 +1444,14 @@ int add_physical_memory_module(ModuleManager& module_manager,
const ModuleId& curr_module,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model) {
const CircuitModelId& sram_model,
const bool& verbose) {
int status = CMD_EXEC_SUCCESS;
std::vector<ModuleId> required_phy_mem_modules;
status = rec_find_physical_memory_children(
static_cast<const ModuleManager&>(module_manager), curr_module,
required_phy_mem_modules);
required_phy_mem_modules, verbose);
if (status != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
}
@ -1463,12 +1466,15 @@ int add_physical_memory_module(ModuleManager& module_manager,
}
std::string phy_mem_module_name = generate_physical_memory_module_name(
module_manager.module_name(curr_module), module_num_config_bits);
VTR_LOGV(verbose, "Adding memory group module '%s' as a child to '%s'...\n",
phy_mem_module_name.c_str(),
module_manager.module_name(curr_module).c_str());
ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name);
if (!module_manager.valid_module_id(phy_mem_module)) {
status = build_memory_group_module(module_manager, decoder_lib, circuit_lib,
sram_orgz_type, phy_mem_module_name,
sram_model, required_phy_mem_modules,
module_num_config_bits);
module_num_config_bits, verbose);
}
if (status != CMD_EXEC_SUCCESS) {
VTR_LOG_ERROR("Failed to create the physical memory module '%s'!\n",

5
openfpga/src/fabric/build_memory_modules.h
View File

@ -37,14 +37,15 @@ int build_memory_group_module(ModuleManager& module_manager,
const std::string& module_name,
const CircuitModelId& sram_model,
const std::vector<ModuleId>& child_modules,
const size_t& num_mems);
const size_t& num_mems, const bool& verbose);
int add_physical_memory_module(ModuleManager& module_manager,
DecoderLibrary& decoder_lib,
const ModuleId& curr_module,
const CircuitLibrary& circuit_lib,
const e_config_protocol_type& sram_orgz_type,
const CircuitModelId& sram_model);
const CircuitModelId& sram_model,
const bool& verbose);
} /* end namespace openfpga */

6
openfpga/src/fabric/build_routing_modules.cpp
View File

@ -490,7 +490,8 @@ static void build_switch_block_module(
/* Build a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, sb_module,
circuit_lib, sram_orgz_type, sram_model);
circuit_lib, sram_orgz_type, sram_model,
verbose);
}
/* Add global ports to the pb_module:
@ -1010,7 +1011,8 @@ static void build_connection_block_module(
/* Build a physical memory block */
if (group_config_block) {
add_physical_memory_module(module_manager, decoder_lib, cb_module,
circuit_lib, sram_orgz_type, sram_model);
circuit_lib, sram_orgz_type, sram_model,
verbose);
}
/* Add global ports to the pb_module:

10
openfpga/src/utils/memory_utils.cpp
View File

@ -499,7 +499,7 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children) {
std::vector<ModuleId>& physical_memory_children, const bool& verbose) {
if (module_manager
.configurable_children(curr_module,
ModuleManager::e_config_child_type::LOGICAL)
@ -522,9 +522,15 @@ int rec_find_physical_memory_children(
physical_memory_children.push_back(
module_manager.logical2physical_configurable_children(
curr_module)[ichild]);
VTR_LOGV(
verbose, "Collecting physical memory module '%s'...\n",
module_manager
.module_name(module_manager.logical2physical_configurable_children(
curr_module)[ichild])
.c_str());
} else {
rec_find_physical_memory_children(module_manager, logical_child,
physical_memory_children);
physical_memory_children, verbose);
}
}
return CMD_EXEC_SUCCESS;

2
openfpga/src/utils/memory_utils.h
View File

@ -61,7 +61,7 @@ size_t estimate_num_configurable_children_to_skip_by_config_protocol(
*/
int rec_find_physical_memory_children(
const ModuleManager& module_manager, const ModuleId& curr_module,
std::vector<ModuleId>& physical_memory_children);
std::vector<ModuleId>& physical_memory_children, const bool& verbose);
/**
* @brief Update all the mappings between logical-to-physical memory children