From 5b6ce1349e027848bc0a35668f543a634da36596 Mon Sep 17 00:00:00 2001
From: Steve Corey <s.corey@utah.edu>
Date: Thu, 5 Jul 2018 11:54:37 -0600
Subject: [PATCH] edited to match vtr_release7 version

---
 tutorial/example_arch.xml | 40 +++++++++++++++++++--------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/tutorial/example_arch.xml b/tutorial/example_arch.xml
index b49e051c1..254ec68fe 100644
--- a/tutorial/example_arch.xml
+++ b/tutorial/example_arch.xml
@@ -2,7 +2,9 @@
  Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
 
  Simple architecture file consisting of clusters of 4 BLEs, each BLE contains a 4-LUT+FF pair.  Delay models from 90nm PTM.
---><architecture>
+-->
+
+<architecture>
 
   <!-- 
        ODIN II specific config begins 
@@ -18,10 +20,10 @@
   <!-- ODIN II specific config ends -->
 
   <!-- Physical descriptions begin -->
-<layout auto="1.0"/>
+<layout auto="1.000000"/>
   <device>
-    <sizing R_minW_nmos="4220.930176" R_minW_pmos="11207.599609"/>
-    <timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="7.247000e-11"/>
+    <sizing R_minW_nmos="4220.930176" R_minW_pmos="11207.599609" ipin_mux_trans_size="0.983352"/>
+    <timing C_ipin_cblock="0.000000e+00" T_ipin_cblock="8.045000e-11"/>
     <area grid_logic_tile_area="2229.320068"/>
     <chan_width_distr>
       <io width="1.000000"/>
@@ -29,12 +31,9 @@
       <y distr="uniform" peak="1.000000"/>
     </chan_width_distr>
     <switch_block type="wilton" fs="3"/>
-  
   </device>
   <switchlist>
     <switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.244000e-11" mux_trans_size="1.835460" buf_size="10.498600"/>
-  <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-        <switch type="mux" name="ipin_cblock" R="1055.232544" Cout="0." Cin="0.000000e+00" Tdel="8.045000e-11" mux_trans_size="0.983352" buf_size="auto"/>
         </switchlist>
   <segmentlist>
     <segment freq="1.000000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
@@ -48,7 +47,7 @@
 
     <!-- Define I/O pads begin -->
     <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <pb_type name="io" capacity="1">
+    <pb_type name="io" capacity="3">
       <input name="outpad" num_pins="1"/>
       <output name="inpad" num_pins="1"/>
       <clock name="clock" num_pins="1"/>
@@ -81,16 +80,12 @@
       </mode>
 
       <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <fc default_in_type="frac" default_in_val="0.15" default_out_type="frac" default_out_val="0.125"/>
+      <fc default_in_type="frac" default_in_val="1.0" default_out_type="frac" default_out_val="0.25"/>
 
       <!-- IOs go on the periphery of the FPGA, for consistency, 
           make it physically equivalent on all sides so that only one definition of I/Os is needed.
           If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
         -->
-
-      <gridlocations>
-          <loc type="perimeter" priority="10"/>
-      </gridlocations>
       <pinlocations pattern="custom">
         <loc side="left">io.outpad io.inpad io.clock</loc>
         <loc side="top">io.outpad io.inpad io.clock</loc>
@@ -99,6 +94,10 @@
       </pinlocations>
 
       <!-- Place I/Os on the sides of the FPGA -->
+      <gridlocations>
+          <loc type="perimeter" priority="10"/>
+      </gridlocations>
+
       <power method="ignore"/>			
     </pb_type>
     <!-- Define I/O pads ends -->
@@ -106,11 +105,9 @@
     <!-- Define general purpose logic block (CLB) begin -->
     <pb_type name="clb">
       <input name="I" num_pins="10" equivalent="true"/>
-      <output name="O" num_pins="4" equivalent="false"/>
+      <output name="O" num_pins="4" equivalent="true"/>
       <clock name="clk" num_pins="1"/>
-      <gridlocations>
-          <loc type="fill" priority="1"/>
-        </gridlocations>
+
       <!-- Describe basic logic element. -->
       <pb_type name="fle" num_pb="4">
         <input name="in" num_pins="4"/>
@@ -168,8 +165,8 @@
       <interconnect>
         <!-- We use a full crossbar to get logical equivalence at inputs of CLB  -->
         <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
-          <delay_constant max="5.735000e-11" in_port="clb.I" out_port="fle[3:0].in"/>
-          <delay_constant max="5.428000e-11" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+          <delay_constant max="5.735000e-11" in_port="clb.I" out_port="fle[3:0].in" />
+          <delay_constant max="5.428000e-11" in_port="fle[3:0].out" out_port="fle[3:0].in" />
         </complete>
         <complete name="clks" input="clb.clk" output="fle[3:0].clk">
         </complete>
@@ -182,8 +179,11 @@
       <pinlocations pattern="spread"/>
 
       <!-- Place this general purpose logic block in any unspecified column -->
+      <gridlocations>
+          <loc type="fill" priority="1"/>
+        </gridlocations>
       </pb_type>
     <!-- Define general purpose logic block (CLB) ends -->
 
   </complexblocklist>
-</architecture>
\ No newline at end of file
+</architecture>