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OpenFPGA
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[core] fixed some bugs

This commit is contained in:
tangxifan 2023-09-25 22:27:24 -07:00
parent 60b8c396dc
commit 5aa206e616
10 changed files with 29 additions and 20 deletions
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4
openfpga/src/fabric/build_device_module.cpp
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@ -125,7 +125,9 @@ int build_device_module_graph(
vpr_device_ctx.grid,
openfpga_ctx.vpr_device_annotation(),
openfpga_ctx.device_rr_gsb(), vpr_device_ctx.rr_graph,
openfpga_ctx.arch().circuit_lib, sram_model,
openfpga_ctx.arch().tile_annotations,
openfpga_ctx.arch().circuit_lib,
sram_model,
openfpga_ctx.arch().config_protocol.type(),
name_module_using_index, frame_view, verbose);
}

1
openfpga/src/fabric/build_grid_module_utils.cpp
View File

@ -98,7 +98,6 @@ void add_grid_module_net_connect_pb_graph_pin(
std::string(grid_type_descriptor->name), pin_info.get_name())) {
/* Exception: use top side for these merged ports */
grid_port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info);
VTR_LOG("Use source pin '%s'\n", grid_port_name.c_str());
}
ModulePortId grid_module_port_id =
module_manager.find_module_port(grid_module, grid_port_name);

19
openfpga/src/fabric/build_tile_modules.cpp
View File

@ -1004,6 +1004,7 @@ static int build_tile_port_and_nets_from_pb(
ModuleManager& module_manager, const ModuleId& tile_module,
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph,
const TileAnnotation& tile_annotation,
const vtr::Point<size_t>& pb_coord, const std::vector<size_t>& pb_instances,
const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id,
const size_t& ipb, const bool& frame_view, const bool& verbose) {
@ -1065,6 +1066,15 @@ static int build_tile_port_and_nets_from_pb(
subtile_index < phy_tile->capacity);
std::string port_name = generate_grid_port_name(
iwidth, iheight, subtile_index, side, pin_info);
if (tile_annotation.is_tile_port_to_merge(
std::string(phy_tile->name),
pin_info.get_name())) {
if (subtile_index == 0) {
port_name = generate_grid_port_name(0, 0, 0, TOP, pin_info);
} else {
continue;
}
}
BasicPort pb_port(port_name, 0, 0);
ModulePortId pb_module_port_id =
module_manager.find_module_port(pb_module, port_name);
@ -1193,6 +1203,7 @@ static int build_tile_module_ports_and_nets(
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id,
const std::vector<size_t>& pb_instances,
const std::map<t_rr_type, std::vector<size_t>>& cb_instances,
@ -1259,7 +1270,7 @@ static int build_tile_module_ports_and_nets(
fabric_tile.pb_coordinates(fabric_tile_id)[ipb];
status_code = build_tile_port_and_nets_from_pb(
module_manager, tile_module, grids, layer, vpr_device_annotation,
rr_graph_view, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb,
rr_graph_view, tile_annotation, pb_coord, pb_instances, fabric_tile, fabric_tile_id, ipb,
frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;
@ -1303,6 +1314,7 @@ static int build_tile_module(
const DeviceGrid& grids, const size_t& layer,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
const bool& name_module_using_index, const bool& frame_view,
@ -1451,7 +1463,7 @@ static int build_tile_module(
/* Add module nets and ports */
status_code = build_tile_module_ports_and_nets(
module_manager, tile_module, grids, layer, vpr_device_annotation,
device_rr_gsb, rr_graph_view, fabric_tile, fabric_tile_id, pb_instances,
device_rr_gsb, rr_graph_view, tile_annotation, fabric_tile, fabric_tile_id, pb_instances,
cb_instances, sb_instances, name_module_using_index, frame_view, verbose);
/* Add global ports to the pb_module:
@ -1521,6 +1533,7 @@ int build_tile_modules(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,
@ -1536,7 +1549,7 @@ int build_tile_modules(ModuleManager& module_manager,
for (FabricTileId fabric_tile_id : fabric_tile.unique_tiles()) {
status_code = build_tile_module(
module_manager, decoder_lib, fabric_tile, fabric_tile_id, grids, layer,
vpr_device_annotation, device_rr_gsb, rr_graph_view, circuit_lib,
vpr_device_annotation, device_rr_gsb, rr_graph_view, tile_annotation, circuit_lib,
sram_model, sram_orgz_type, name_module_using_index, frame_view, verbose);
if (status_code != CMD_EXEC_SUCCESS) {
return CMD_EXEC_FATAL_ERROR;

2
openfpga/src/fabric/build_tile_modules.h
View File

@ -16,6 +16,7 @@
#include "module_manager.h"
#include "rr_graph_view.h"
#include "vpr_device_annotation.h"
#include "tile_annotation.h"
/********************************************************************
* Function declaration
@ -30,6 +31,7 @@ int build_tile_modules(ModuleManager& module_manager,
const VprDeviceAnnotation& vpr_device_annotation,
const DeviceRRGSB& device_rr_gsb,
const RRGraphView& rr_graph_view,
const TileAnnotation& tile_annotation,
const CircuitLibrary& circuit_lib,
const CircuitModelId& sram_model,
const e_config_protocol_type& sram_orgz_type,

2
openfpga/src/fabric/build_top_module_child_tile_instance.cpp
View File

@ -1406,7 +1406,7 @@ static int build_top_module_global_net_for_given_tile_module(
subtile_index, pin_side, grid_pin_info);
if (tile_annotation.is_tile_port_to_merge(
std::string(physical_tile->name), grid_pin_info.get_name())) {
if (subtile_index != 0) {
if (subtile_index == 0) {
grid_port_name =
generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
} else {

2
openfpga/src/fabric/build_top_module_connection.cpp
View File

@ -952,7 +952,7 @@ static int build_top_module_global_net_for_given_grid_module(
subtile_index, pin_side, grid_pin_info);
if (tile_annotation.is_tile_port_to_merge(
std::string(physical_tile->name), grid_pin_info.get_name())) {
if (subtile_index != 0) {
if (subtile_index == 0) {
grid_port_name =
generate_grid_port_name(0, 0, 0, TOP, grid_pin_info);
} else {

12
openfpga_flow/openfpga_shell_scripts/global_tile_clock_duplicated_pins_full_testbench_example_script.openfpga → openfpga_flow/openfpga_shell_scripts/global_tile_clock_options_full_testbench_example_script.openfpga
View File

@ -23,7 +23,7 @@ lut_truth_table_fixup
# Build the module graph
# - Enabled compression on routing architecture modules
# - Enable pin duplication on grid modules
build_fabric --compress_routing --duplicate_grid_pin #--verbose
build_fabric --compress_routing ${OPENFPGA_GROUP_CONFIG_BLOCK_OPTIONS} ${OPENFPGA_GROUP_TILE_CONFIG_OPTIONS} #--verbose
# Write the fabric hierarchy of module graph to a file
# This is used by hierarchical PnR flows
@ -56,16 +56,6 @@ write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --pri
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit
# Write the SDC files for PnR backend
# - Turn on every options here
write_pnr_sdc --file ./SDC
# Write SDC to disable timing for configure ports
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
# Write the SDC to run timing analysis for a mapped FPGA fabric
write_analysis_sdc --file ./SDC_analysis
# Finish and exit OpenFPGA
exit

2
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -212,7 +212,7 @@ echo -e "Testing global port definition from tiles";
run-task basic_tests/global_tile_ports/global_tile_clock $@
run-task basic_tests/global_tile_ports/global_tile_clock_subtile $@
run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge $@
run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_duplicate_pin $@
run-task basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config $@
run-task basic_tests/global_tile_ports/global_tile_reset $@
run-task basic_tests/global_tile_ports/global_tile_4clock $@
run-task basic_tests/global_tile_ports/global_tile_4clock_pin $@

4
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_duplicate_pin/config/task.conf → openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config/config/task.conf
View File

@ -16,10 +16,12 @@ timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_duplicated_pins_full_testbench_example_script.openfpga
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_options_full_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkMergeSubtilePort_registerable_io_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=2x2_hybrid_io
openfpga_group_tile_config_options=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_group_config_block_options=--group_config_block
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml

1
openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_clock_subtile_port_merge_fabric_tile_group_config/config/tile_config.xml Normal file
View File

@ -0,0 +1 @@
<tiles style="top_left"/>