[Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised
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@ -2,8 +2,8 @@
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// Reference:
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// Reference:
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// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
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// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
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module fifo
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module fifo
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#( parameter ADDRESS_WIDTH = 12, // number of words in ram
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#( parameter ADDRESS_WIDTH = 4, // number of words in ram
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DATA_WIDTH = 8 // number of bits in word
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DATA_WIDTH = 4 // number of bits in word
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)
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)
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// IO ports
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// IO ports
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@ -94,4 +94,4 @@ module fifo
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// assign full/empty status to output ports
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// assign full/empty status to output ports
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assign full = full_reg;
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assign full = full_reg;
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assign empty = empty_reg;
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assign empty = empty_reg;
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endmodule
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endmodule
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@ -2,8 +2,8 @@
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// Reference:
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// Reference:
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// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
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// https://embeddedthoughts.com/2016/07/13/fifo-buffer-using-block-ram-on-a-xilinx-spartan-3-fpga/
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module sync_dual_port_ram
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module sync_dual_port_ram
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#( parameter ADDRESS_WIDTH = 12, // number of words in ram
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#( parameter ADDRESS_WIDTH = 4, // number of words in ram
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DATA_WIDTH = 8 // number of bits in word
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DATA_WIDTH = 4 // number of bits in word
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)
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)
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// IO ports
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// IO ports
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@ -32,4 +32,4 @@ module sync_dual_port_ram
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// assignments for two data out ports
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// assignments for two data out ports
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assign read_data_out = ram[read_address_reg];
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assign read_data_out = ram[read_address_reg];
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assign write_data_out = ram[write_address_reg];
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assign write_data_out = ram[write_address_reg];
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endmodule
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endmodule
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