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Merge pull request #1400 from lnis-uofu/xt_fbit_writer 

Multiple improvements on Fabric Bitstream Writer
This commit is contained in:
tangxifan 2023-10-06 22:51:22 -07:00 committed by GitHub
parent 78373be86d 5b8a51d3f6
commit 5a7a569ce3
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GPG Key ID: 4AEE18F83AFDEB23
26 changed files with 789 additions and 57 deletions
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34
docs/source/manual/openfpga_shell/openfpga_commands/fpga_bitstream_commands.rst
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@ -81,6 +81,40 @@ write_fabric_bitstream
Specify the file format [``plain_text`` | ``xml``]. By default is ``plain_text``.
See file formats in :ref:`file_formats_fabric_bitstream_xml` and :ref:`file_formats_fabric_bitstream_plain_text`.
.. option:: --filter_value <int>
.. warning:: Value filter is only applicable to XML file format!
Specify the value to be keep in the bitstream file. Can be [``0`` | ``1`` ]. By default is ``none``, which means no filter is applied.
When specified, only the bit with the filter value is written to the file.
See file formats in :ref:`file_formats_fabric_bitstream_xml`.
.. option:: --path_only
.. warning:: This is only applicable to XML file format!
Specify that only the ``path`` attribute is kept in the bitstream file. By default is ``off``.
When specified, only the ``path`` attribute is written to the file.
Regarding the ``path`` attribute, See file formats in :ref:`file_formats_fabric_bitstream_xml`.
.. option:: --value_only
.. warning:: This is only applicable to XML file format!
Specify that only the ``value`` attribute is kept in the bitstream file. By default is ``off``.
When specified, only the ``value`` attribute is written to the file.
Regarding the ``value`` attribute, see file formats in :ref:`file_formats_fabric_bitstream_xml`.
.. option:: --trim_path
.. warning:: This is only applicable to XML file format!
.. warning:: This is an option for power user! Suggest only to use when you enable the ``--group_config_block`` option when building a fabric (See details in :ref:`cmd_build_fabric`).
Specify that the ``path`` will be trimed by 1 level in resulting bitstream file. By default is ``off``.
When specified, the hierarchy of ``path`` will be reduced by 1. For example, the original path is ``fpga_top.tile_1__1_.config_block.sub_mem.mem_out[0]``, the path after trimming is ``fpga_top.tile_1__1_.config_block.mem_out[0]``.
Regarding the ``path`` attribute, see file formats in :ref:`file_formats_fabric_bitstream_xml`.
.. option:: --fast_configuration
Reduce the bitstream size when outputing by skipping dummy configuration bits. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal.

23
libs/libfpgabitstream/src/bitstream_manager_utils.cpp
View File

@ -81,6 +81,29 @@ size_t find_bitstream_manager_config_bit_index_in_parent_block(
return curr_index;
}
/********************************************************************
* Find the index of a configuration bit in the children bits of its grandparent
*block. We count the index from the parent of current parent block
*******************************************************************/
size_t find_bitstream_manager_config_bit_index_in_grandparent_block(
const BitstreamManager& bitstream_manager, const ConfigBitId& bit_id) {
size_t curr_index = 0;
ConfigBlockId parent_blk = bitstream_manager.bit_parent_block(bit_id);
ConfigBlockId grandparent_blk = bitstream_manager.block_parent(parent_blk);
for (const ConfigBlockId& cand_blk :
bitstream_manager.block_children(grandparent_blk)) {
if (cand_blk != parent_blk) {
curr_index += bitstream_manager.block_bits(cand_blk).size();
} else {
curr_index += find_bitstream_manager_config_bit_index_in_parent_block(
bitstream_manager, bit_id);
break;
}
}
return curr_index;
}
/********************************************************************
* Find the total number of configuration bits under a block
* As configuration bits are stored only under the leaf blocks,

3
libs/libfpgabitstream/src/bitstream_manager_utils.h
View File

@ -25,6 +25,9 @@ std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(
size_t find_bitstream_manager_config_bit_index_in_parent_block(
const BitstreamManager& bitstream_manager, const ConfigBitId& bit_id);
size_t find_bitstream_manager_config_bit_index_in_grandparent_block(
const BitstreamManager& bitstream_manager, const ConfigBitId& bit_id);
size_t rec_find_bitstream_manager_block_sum_of_bits(
const BitstreamManager& bitstream_manager, const ConfigBlockId& block);

21
openfpga/src/base/openfpga_bitstream_command_template.h
View File

@ -190,6 +190,27 @@ ShellCommandId add_write_fabric_bitstream_command_template(
"file format of fabric bitstream [plain_text|xml]. Default: plain_text");
shell_cmd.set_option_require_value(opt_file_format, openfpga::OPT_STRING);
CommandOptionId opt_filter_value = shell_cmd.add_option(
"filter_value", false,
"Specify what values should be written out in the resulting fabric "
"bitstream [0|1|none]. Only applicable to XML file format. Default: none");
shell_cmd.set_option_require_value(opt_filter_value, openfpga::OPT_STRING);
shell_cmd.add_option(
"path_only", false,
"Only paths will be written out in the resulting fabric bitstream. Only "
"applicable to XML file format. Default: off");
shell_cmd.add_option(
"value_only", false,
"Only values will be written out in the resulting fabric bitstream. Only "
"applicable to XML file format. Default: off");
shell_cmd.add_option(
"trim_path", false,
"Trim the path by a level of 1 in the resulting fabric bitstream. Only "
"applicable to XML file format. Default: off");
/* Add an option '--fast_configuration' */
shell_cmd.add_option("fast_configuration", false,
"Reduce the size of bitstream to be downloaded");

53
openfpga/src/base/openfpga_bitstream_template.h
View File

@ -4,6 +4,7 @@
/********************************************************************
* This file includes functions to build bitstream database
*******************************************************************/
#include "bitstream_writer_options.h"
#include "build_device_bitstream.h"
#include "build_fabric_bitstream.h"
#include "build_io_mapping_info.h"
@ -94,6 +95,10 @@ int write_fabric_bitstream_template(const T& openfpga_ctx, const Command& cmd,
CommandOptionId opt_keep_dont_care_bits = cmd.option("keep_dont_care_bits");
CommandOptionId opt_wl_decremental_order = cmd.option("wl_decremental_order");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_filter_value = cmd.option("filter_value");
CommandOptionId opt_path_only = cmd.option("path_only");
CommandOptionId opt_value_only = cmd.option("value_only");
CommandOptionId opt_trim_path = cmd.option("trim_path");
/* Write fabric bitstream if required */
int status = CMD_EXEC_SUCCESS;
@ -112,26 +117,50 @@ int write_fabric_bitstream_template(const T& openfpga_ctx, const Command& cmd,
file_format = cmd_context.option_value(cmd, opt_file_format);
}
if (std::string("xml") == file_format) {
/* Validate options */
BitstreamWriterOption bitfile_writer_opt;
bitfile_writer_opt.set_output_file_type(file_format);
bitfile_writer_opt.set_output_file_name(
cmd_context.option_value(cmd, opt_file));
bitfile_writer_opt.set_time_stamp(
!cmd_context.option_enable(cmd, opt_no_time_stamp));
bitfile_writer_opt.set_verbose_output(
cmd_context.option_enable(cmd, opt_verbose));
bitfile_writer_opt.set_trim_path(
cmd_context.option_enable(cmd, opt_trim_path));
bitfile_writer_opt.set_path_only(
cmd_context.option_enable(cmd, opt_path_only));
bitfile_writer_opt.set_value_only(
cmd_context.option_enable(cmd, opt_value_only));
bitfile_writer_opt.set_fast_configuration(
cmd_context.option_enable(cmd, opt_fast_config));
bitfile_writer_opt.set_keep_dont_care_bits(
cmd_context.option_enable(cmd, opt_keep_dont_care_bits));
bitfile_writer_opt.set_wl_decremental_order(
cmd_context.option_enable(cmd, opt_wl_decremental_order));
if (cmd_context.option_enable(cmd, opt_filter_value)) {
bitfile_writer_opt.set_filter_value(
cmd_context.option_value(cmd, opt_filter_value));
}
if (!bitfile_writer_opt.validate(true)) {
VTR_LOG_ERROR("Conflicts detected in options for bitstream writer!\n");
return CMD_EXEC_FATAL_ERROR;
}
if (bitfile_writer_opt.output_file_type() ==
BitstreamWriterOption::e_bitfile_type::XML) {
status = write_fabric_bitstream_to_xml_file(
openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(),
openfpga_ctx.arch().config_protocol,
cmd_context.option_value(cmd, opt_file),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
openfpga_ctx.arch().config_protocol, bitfile_writer_opt);
} else {
VTR_ASSERT_SAFE(bitfile_writer_opt.output_file_type() ==
BitstreamWriterOption::e_bitfile_type::TEXT);
/* By default, output in plain text format */
status = write_fabric_bitstream_to_text_file(
openfpga_ctx.bitstream_manager(), openfpga_ctx.fabric_bitstream(),
openfpga_ctx.blwl_shift_register_banks(),
openfpga_ctx.arch().config_protocol,
openfpga_ctx.fabric_global_port_info(),
cmd_context.option_value(cmd, opt_file),
cmd_context.option_enable(cmd, opt_fast_config),
cmd_context.option_enable(cmd, opt_keep_dont_care_bits),
!cmd_context.option_enable(cmd, opt_wl_decremental_order),
!cmd_context.option_enable(cmd, opt_no_time_stamp),
cmd_context.option_enable(cmd, opt_verbose));
openfpga_ctx.fabric_global_port_info(), bitfile_writer_opt);
}
return status;

197
openfpga/src/fpga_bitstream/bitstream_writer_options.cpp Normal file
View File

@ -0,0 +1,197 @@
/******************************************************************************
* Memember functions for data structure BitstreamWriterOption
******************************************************************************/
#include "bitstream_writer_options.h"
#include "vtr_assert.h"
#include "vtr_log.h"
/* begin namespace openfpga */
namespace openfpga {
/**************************************************
* Public Constructors
*************************************************/
BitstreamWriterOption::BitstreamWriterOption() {
file_type_ = BitstreamWriterOption::e_bitfile_type::NUM_TYPES;
BITFILE_TYPE_STRING_ = {"plain_text", "xml"};
output_file_.clear();
time_stamp_ = true;
verbose_output_ = false;
filter_value_ = "";
trim_path_ = false;
path_only_ = false;
value_only_ = false;
fast_config_ = false;
keep_dont_care_bits_ = false;
wl_decremental_order_ = false;
}
/**************************************************
* Public Accessors
*************************************************/
BitstreamWriterOption::e_bitfile_type BitstreamWriterOption::output_file_type()
const {
return file_type_;
}
std::string BitstreamWriterOption::output_file_name() const {
return output_file_;
}
bool BitstreamWriterOption::time_stamp() const { return time_stamp_; }
bool BitstreamWriterOption::verbose_output() const { return verbose_output_; }
bool BitstreamWriterOption::filter_value() const {
return !filter_value_.empty();
}
bool BitstreamWriterOption::value_to_skip(const size_t& val) const {
return std::to_string(val) == filter_value_;
}
bool BitstreamWriterOption::trim_path() const { return trim_path_; }
bool BitstreamWriterOption::output_path() const {
if (!path_only_ && !value_only_) {
return true;
}
return path_only_;
}
bool BitstreamWriterOption::output_value() const {
if (!path_only_ && !value_only_) {
return true;
}
return value_only_;
}
bool BitstreamWriterOption::fast_configuration() const { return fast_config_; }
bool BitstreamWriterOption::keep_dont_care_bits() const {
return keep_dont_care_bits_;
}
bool BitstreamWriterOption::wl_decremental_order() const {
return wl_decremental_order_;
}
/******************************************************************************
* Private Mutators
******************************************************************************/
void BitstreamWriterOption::set_output_file_type(const std::string& val) {
file_type_ = str2bitfile_type(val);
}
void BitstreamWriterOption::set_output_file_name(
const std::string& output_file) {
output_file_ = output_file;
}
void BitstreamWriterOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void BitstreamWriterOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}
void BitstreamWriterOption::set_filter_value(const std::string& val) {
filter_value_ = val;
}
void BitstreamWriterOption::set_trim_path(const bool& enabled) {
trim_path_ = enabled;
}
void BitstreamWriterOption::set_path_only(const bool& enabled) {
path_only_ = enabled;
}
void BitstreamWriterOption::set_value_only(const bool& enabled) {
value_only_ = enabled;
}
void BitstreamWriterOption::set_fast_configuration(const bool& enabled) {
fast_config_ = enabled;
}
void BitstreamWriterOption::set_keep_dont_care_bits(const bool& enabled) {
keep_dont_care_bits_ = enabled;
}
void BitstreamWriterOption::set_wl_decremental_order(const bool& enabled) {
wl_decremental_order_ = enabled;
}
bool BitstreamWriterOption::validate(bool show_err_msg) const {
/* Check file type */
if (!valid_file_type(file_type_)) {
VTR_LOGV_ERROR(show_err_msg, "Invalid file type!\n");
return false;
}
if (output_file_.empty()) {
VTR_LOGV_ERROR(show_err_msg, "Empty file name!\n");
return false;
}
if (file_type_ == BitstreamWriterOption::e_bitfile_type::XML) {
/* All the options in the XML format should be off */
if (path_only_ && value_only_) {
VTR_LOGV_ERROR(show_err_msg,
"Both path and value are specifed as only inputs! If "
"specified, please define one of them\n");
return false;
}
if (!filter_value_.empty() && (filter_value_ != std::to_string(0) &&
filter_value_ != std::to_string(1))) {
VTR_LOGV_ERROR(show_err_msg,
"Invalid value '%s' for filter values. Expect [0|1]!\n",
filter_value_.c_str());
return false;
}
}
return true;
}
BitstreamWriterOption::e_bitfile_type BitstreamWriterOption::str2bitfile_type(
const std::string& type_str, const bool& verbose) const {
for (int itype = size_t(BitstreamWriterOption::e_bitfile_type::TEXT);
itype != size_t(BitstreamWriterOption::e_bitfile_type::NUM_TYPES);
++itype) {
if (type_str == std::string(BITFILE_TYPE_STRING_[itype])) {
return static_cast<BitstreamWriterOption::e_bitfile_type>(itype);
}
}
VTR_LOGV_ERROR(verbose, "Invalid type for bitstream file! Expect %s\n",
bitfile_type_all2str().c_str());
return BitstreamWriterOption::e_bitfile_type::NUM_TYPES;
}
std::string BitstreamWriterOption::bitfile_type2str(
const BitstreamWriterOption::e_bitfile_type& type,
const bool& verbose) const {
if (!valid_file_type(type)) {
VTR_LOGV_ERROR(verbose, "Invalid type for bitstream file! Expect %s\n",
bitfile_type_all2str().c_str());
return std::string();
}
return std::string(BITFILE_TYPE_STRING_[size_t(type)]);
}
std::string BitstreamWriterOption::bitfile_type_all2str() const {
std::string full_types = "[";
for (int itype = size_t(BitstreamWriterOption::e_bitfile_type::TEXT);
itype != size_t(BitstreamWriterOption::e_bitfile_type::NUM_TYPES);
++itype) {
full_types += std::string(BITFILE_TYPE_STRING_[itype]) + std::string("|");
}
full_types.pop_back();
full_types += "]";
return full_types;
}
bool BitstreamWriterOption::valid_file_type(
const BitstreamWriterOption::e_bitfile_type& bitfile_type) const {
return bitfile_type != BitstreamWriterOption::e_bitfile_type::NUM_TYPES;
}
} /* end namespace openfpga */

104
openfpga/src/fpga_bitstream/bitstream_writer_options.h Normal file
View File

@ -0,0 +1,104 @@
#ifndef BITSTREAM_WRITER_OPTIONS_H
#define BITSTREAM_WRITER_OPTIONS_H
/********************************************************************
* Include header files required by the data structure definition
*******************************************************************/
#include <array>
#include <string>
/* Begin namespace openfpga */
namespace openfpga {
/********************************************************************
* Options for Bitstream Writer
*******************************************************************/
class BitstreamWriterOption {
public: /* Private data structures */
/* A type to define the bitstream file format */
enum class e_bitfile_type { TEXT, XML, NUM_TYPES };
public: /* Public constructor */
/* Set default options */
BitstreamWriterOption();
public: /* Public accessors */
e_bitfile_type output_file_type() const;
std::string output_file_name() const;
bool time_stamp() const;
bool verbose_output() const;
/* Check if a filter on value is applied */
bool filter_value() const;
/* Check if a given value should be skipped */
bool value_to_skip(const size_t& val) const;
/* Check if path trimming should be applied or not */
bool trim_path() const;
/* Check if path should be outputted in the resulting file */
bool output_path() const;
/* Check if value should be outputted in the resulting file */
bool output_value() const;
bool fast_configuration() const;
bool keep_dont_care_bits() const;
bool wl_decremental_order() const;
public: /* Public mutators */
void set_output_file_type(const std::string& val);
void set_output_file_name(const std::string& output_file);
void set_time_stamp(const bool& enabled);
void set_verbose_output(const bool& enabled);
void set_trim_path(const bool& enabled);
void set_path_only(const bool& enabled);
void set_value_only(const bool& enabled);
void set_fast_configuration(const bool& enabled);
void set_keep_dont_care_bits(const bool& enabled);
void set_wl_decremental_order(const bool& enabled);
void set_filter_value(const std::string& val);
public: /* Public validator */
bool validate(bool show_err_msg = false) const;
public: /* Internal utility */
/** @brief Parse the file type from string to valid type. Parser
* error can be turned on */
e_bitfile_type str2bitfile_type(const std::string& type_str,
const bool& verbose = false) const;
/** @brief Output the string representing file_type */
std::string bitfile_type2str(const e_bitfile_type& type,
const bool& verbose = false) const;
/** @brief Validate the file_type */
bool valid_file_type(const e_bitfile_type& bitfile_type) const;
/* Generate a string include all the valid style
* Useful for printing debugging messages */
std::string bitfile_type_all2str() const;
private: /* Internal Data */
/* Universal options */
e_bitfile_type file_type_;
std::string output_file_;
bool time_stamp_;
bool verbose_output_;
/* XML-specific options */
std::string filter_value_;
bool trim_path_;
bool path_only_;
bool value_only_;
/* Plain-text options */
bool fast_config_;
bool keep_dont_care_bits_;
bool wl_decremental_order_;
/* Constants */
std::array<const char*, size_t(e_bitfile_type::NUM_TYPES)>
BITFILE_TYPE_STRING_;
};
} /* End namespace openfpga*/
#endif

29
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -579,10 +579,11 @@ int write_fabric_bitstream_to_text_file(
const FabricBitstream& fabric_bitstream,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ConfigProtocol& config_protocol,
const FabricGlobalPortInfo& global_ports, const std::string& fname,
const bool& fast_configuration, const bool& keep_dont_care_bits,
const bool& wl_incremental_order, const bool& include_time_stamp,
const bool& verbose) {
const FabricGlobalPortInfo& global_ports,
const BitstreamWriterOption& options) {
VTR_ASSERT(options.output_file_type() ==
BitstreamWriterOption::e_bitfile_type::TEXT);
std::string fname = options.output_file_name();
/* Ensure that we have a valid file name */
if (true == fname.empty()) {
VTR_LOG_ERROR(
@ -603,8 +604,10 @@ int write_fabric_bitstream_to_text_file(
check_file_stream(fname.c_str(), fp);
bool apply_fast_configuration =
is_fast_configuration_applicable(global_ports) && fast_configuration;
if (fast_configuration && apply_fast_configuration != fast_configuration) {
is_fast_configuration_applicable(global_ports) &&
options.fast_configuration();
if (options.fast_configuration() &&
apply_fast_configuration != options.fast_configuration()) {
VTR_LOG_WARN("Disable fast configuration even it is enabled by user\n");
}
@ -616,7 +619,7 @@ int write_fabric_bitstream_to_text_file(
}
/* Write file head */
write_fabric_bitstream_text_file_head(fp, include_time_stamp);
write_fabric_bitstream_text_file_head(fp, options.time_stamp());
/* Output fabric bitstream to the file */
int status = 0;
@ -649,19 +652,18 @@ int write_fabric_bitstream_to_text_file(
// bitstream
status = fast_write_memory_bank_flatten_fabric_bitstream_to_text_file(
fp, apply_fast_configuration, bit_value_to_skip, fabric_bitstream,
keep_dont_care_bits, wl_incremental_order);
options.keep_dont_care_bits(), options.wl_decremental_order());
} else if (BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type()) {
status = write_memory_bank_flatten_fabric_bitstream_to_text_file(
fp, apply_fast_configuration, bit_value_to_skip, fabric_bitstream,
keep_dont_care_bits);
options.keep_dont_care_bits());
} else {
VTR_ASSERT(BLWL_PROTOCOL_SHIFT_REGISTER ==
config_protocol.bl_protocol_type());
status = write_memory_bank_shift_register_fabric_bitstream_to_text_file(
fp, apply_fast_configuration, bit_value_to_skip,
fabric_bitstream, blwl_sr_banks, keep_dont_care_bits);
fp, apply_fast_configuration, bit_value_to_skip, fabric_bitstream,
blwl_sr_banks, options.keep_dont_care_bits());
}
break;
}
@ -685,7 +687,8 @@ int write_fabric_bitstream_to_text_file(
/* Close file handler */
fp.close();
VTR_LOGV(verbose, "Outputted %lu configuration bits to plain text file: %s\n",
VTR_LOGV(options.verbose_output(),
"Outputted %lu configuration bits to plain text file: %s\n",
fabric_bitstream.bits().size(), fname.c_str());
return status;

7
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.h
View File

@ -8,6 +8,7 @@
#include <vector>
#include "bitstream_manager.h"
#include "bitstream_writer_options.h"
#include "config_protocol.h"
#include "fabric_bitstream.h"
#include "fabric_global_port_info.h"
@ -25,10 +26,8 @@ int write_fabric_bitstream_to_text_file(
const FabricBitstream& fabric_bitstream,
const MemoryBankShiftRegisterBanks& blwl_sr_banks,
const ConfigProtocol& config_protocol,
const FabricGlobalPortInfo& global_ports, const std::string& fname,
const bool& fast_configuration, const bool& keep_dont_care_bits,
const bool& wl_incremental_order, const bool& include_time_stamp,
const bool& verbose);
const FabricGlobalPortInfo& global_ports,
const BitstreamWriterOption& options);
} /* end namespace openfpga */

52
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
View File

@ -72,36 +72,57 @@ static int write_fabric_config_bit_to_xml_file(
std::fstream& fp, const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream, const FabricBitId& fabric_bit,
const e_config_protocol_type& config_type, bool fast_xml,
const int& xml_hierarchy_depth, std::string& bl_addr, std::string& wl_addr) {
const int& xml_hierarchy_depth, std::string& bl_addr, std::string& wl_addr,
const BitstreamWriterOption& options) {
if (false == valid_file_stream(fp)) {
return 1;
}
if (options.value_to_skip(
bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit)))) {
return 0;
}
write_tab_to_file(fp, xml_hierarchy_depth);
fp << "<bit id=\"" << size_t(fabric_bit) << "\"";
if (options.output_value()) {
fp << " value=\"";
fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit));
fp << "\"";
}
/* Output hierarchy of this parent*/
const ConfigBitId& config_bit = fabric_bitstream.config_bit(fabric_bit);
const ConfigBlockId& config_block =
bitstream_manager.bit_parent_block(config_bit);
if (options.output_path()) {
std::vector<ConfigBlockId> block_hierarchy =
find_bitstream_manager_block_hierarchy(bitstream_manager, config_block);
std::string hie_path;
for (const ConfigBlockId& temp_block : block_hierarchy) {
hie_path += bitstream_manager.block_name(temp_block);
for (size_t iblk = 0; iblk < block_hierarchy.size(); ++iblk) {
/* If enabled, pop the last block name */
if (options.trim_path() && iblk == block_hierarchy.size() - 1) {
break;
}
hie_path += bitstream_manager.block_name(block_hierarchy[iblk]);
hie_path += std::string(".");
}
hie_path += generate_configurable_memory_data_out_name();
hie_path += std::string("[");
hie_path +=
std::to_string(find_bitstream_manager_config_bit_index_in_parent_block(
bitstream_manager, config_bit));
size_t bit_idx_in_parent_block =
find_bitstream_manager_config_bit_index_in_parent_block(bitstream_manager,
config_bit);
if (options.trim_path()) {
bit_idx_in_parent_block =
find_bitstream_manager_config_bit_index_in_grandparent_block(
bitstream_manager, config_bit);
}
hie_path += std::to_string(bit_idx_in_parent_block);
hie_path += std::string("]");
fp << " path=\"" << hie_path << "\">\n";
fp << " path=\"" << hie_path << "\"";
}
fp << ">\n";
switch (config_type) {
case CONFIG_MEM_STANDALONE:
@ -196,7 +217,7 @@ static int write_fabric_regional_config_bit_to_xml_file(
const FabricBitstream& fabric_bitstream,
const FabricBitRegionId& fabric_region,
const e_config_protocol_type& config_type, bool fast_xml,
const int& xml_hierarchy_depth) {
const int& xml_hierarchy_depth, const BitstreamWriterOption& options) {
if (false == valid_file_stream(fp)) {
return 1;
}
@ -228,7 +249,7 @@ static int write_fabric_regional_config_bit_to_xml_file(
fabric_bitstream.region_bits(fabric_region)) {
status = write_fabric_config_bit_to_xml_file(
fp, bitstream_manager, fabric_bitstream, fabric_bit, config_type,
fast_xml, xml_hierarchy_depth + 1, bl_addr, wl_addr);
fast_xml, xml_hierarchy_depth + 1, bl_addr, wl_addr, options);
if (1 == status) {
return status;
}
@ -261,9 +282,11 @@ static int write_fabric_regional_config_bit_to_xml_file(
int write_fabric_bitstream_to_xml_file(
const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol, const std::string& fname,
const bool& include_time_stamp, const bool& verbose) {
const ConfigProtocol& config_protocol, const BitstreamWriterOption& options) {
VTR_ASSERT(options.output_file_type() ==
BitstreamWriterOption::e_bitfile_type::XML);
/* Ensure that we have a valid file name */
std::string fname = options.output_file_name();
if (true == fname.empty()) {
VTR_LOG_ERROR(
"Received empty file name to output bitstream!\n\tPlease specify a valid "
@ -282,7 +305,7 @@ int write_fabric_bitstream_to_xml_file(
check_file_stream(fname.c_str(), fp);
/* Write XML head */
write_fabric_bitstream_xml_file_head(fp, include_time_stamp);
write_fabric_bitstream_xml_file_head(fp, options.time_stamp());
int xml_hierarchy_depth = 0;
fp << "<fabric_bitstream>\n";
@ -294,7 +317,7 @@ int write_fabric_bitstream_to_xml_file(
fp, bitstream_manager, fabric_bitstream, region, config_protocol.type(),
BLWL_PROTOCOL_FLATTEN == config_protocol.bl_protocol_type() &&
BLWL_PROTOCOL_FLATTEN == config_protocol.wl_protocol_type(),
xml_hierarchy_depth + 1);
xml_hierarchy_depth + 1, options);
if (1 == status) {
break;
}
@ -306,7 +329,8 @@ int write_fabric_bitstream_to_xml_file(
/* Close file handler */
fp.close();
VTR_LOGV(verbose, "Outputted %lu configuration bits to XML file: %s\n",
VTR_LOGV(options.verbose_output(),
"Outputted %lu configuration bits to XML file: %s\n",
fabric_bitstream.bits().size(), fname.c_str());
return status;

4
openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.h
View File

@ -8,6 +8,7 @@
#include <vector>
#include "bitstream_manager.h"
#include "bitstream_writer_options.h"
#include "config_protocol.h"
#include "fabric_bitstream.h"
@ -21,8 +22,7 @@ namespace openfpga {
int write_fabric_bitstream_to_xml_file(
const BitstreamManager& bitstream_manager,
const FabricBitstream& fabric_bitstream,
const ConfigProtocol& config_protocol, const std::string& fname,
const bool& include_time_stamp, const bool& verbose);
const ConfigProtocol& config_protocol, const BitstreamWriterOption& options);
} /* end namespace openfpga */

2
openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
View File

@ -45,7 +45,7 @@ build_architecture_bitstream --verbose --write_file fabric_independent_bitstream
build_fabric_bitstream --verbose
# Write fabric-dependent bitstream
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text
write_fabric_bitstream --file fabric_bitstream.xml --format xml ${OPENFPGA_FABRIC_BITSTREAM_OPTIONS}
# Write the Verilog netlist for FPGA fabric
# - Enable the use of explicit port mapping in Verilog netlist

7
openfpga_flow/regression_test_scripts/fpga_bitstream_reg_test.sh
View File

@ -45,3 +45,10 @@ run-task fpga_bitstream/report_bitstream_distribution/custom_depth $@
echo -e "Testing bitstream file with don't care bits";
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_flatten $@
run-task fpga_bitstream/dont_care_bits/ql_memory_bank_shift_register $@
echo -e "Testing bitstream file with selective contents";
run-task fpga_bitstream/trim_path $@
run-task fpga_bitstream/filter_value0 $@
run-task fpga_bitstream/filter_value1 $@
run-task fpga_bitstream/path_only $@
run-task fpga_bitstream/value_only $@

1
openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile/config/task.conf
View File

@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml

1
openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_hetero_fabric_tile_Lshape/config/task.conf
View File

@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileableL_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml

1
openfpga_flow/tasks/basic_tests/group_config_block/group_config_block_homo_fabric_tile_global_tile_clock_io_subtile/config/task.conf
View File

@ -26,6 +26,7 @@ openfpga_vpr_route_chan_width=20
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml

56
openfpga_flow/tasks/fpga_bitstream/filter_value0/config/task.conf Normal file
View File

@ -0,0 +1,56 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=--filter_value 0
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/fpga_bitstream/filter_value0/config/tile_config.xml Normal file
View File

@ -0,0 +1 @@
<tiles style="top_left"/>

56
openfpga_flow/tasks/fpga_bitstream/filter_value1/config/task.conf Normal file
View File

@ -0,0 +1,56 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=--filter_value 1
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/fpga_bitstream/filter_value1/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

56
openfpga_flow/tasks/fpga_bitstream/path_only/config/task.conf Normal file
View File

@ -0,0 +1,56 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=--path_only
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/fpga_bitstream/path_only/config/tile_config.xml Normal file
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@ -0,0 +1 @@
<tiles style="top_left"/>

56
openfpga_flow/tasks/fpga_bitstream/trim_path/config/task.conf Normal file
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@ -0,0 +1,56 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=--trim_path
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

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<tiles style="top_left"/>

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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_config_block_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_dsp8_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=--constant_net_method route --skip_sync_clustering_and_routing_results on
openfpga_pb_pin_fixup_command = pb_pin_fixup --verbose
openfpga_vpr_device=3x2
openfpga_vpr_route_chan_width=60
openfpga_group_tile_config_option=--group_tile ${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=
openfpga_add_fpga_core_module=
openfpga_fabric_bitstream_options=--value_only
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_2/mac_2.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_4/mac_4.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_6/mac_6.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/mac/mac_8/mac_8.v
[SYNTHESIS_PARAM]
# Yosys script parameters
bench_yosys_cell_sim_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_cell_sim.v
bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm_dsp_map.v
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench0_top = mac_2
bench1_top = mac_4
bench2_top = mac_6
bench3_top = mac_8
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist=

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<tiles style="top_left"/>