From 5a40c6713d2be95dd9690d4e9e2485a13b9e3d5d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 21 Aug 2019 21:50:26 -0600 Subject: [PATCH] managed to plug in refactored essential gates, dead codes to be removed --- .travis/script.sh | 2 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 9 +++++++-- .../fpga_x2p/verilog/verilog_essential_gates.cpp | 16 ++++++++-------- .../fpga_x2p/verilog/verilog_submodule_utils.cpp | 4 ++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 ++ 5 files changed, 20 insertions(+), 13 deletions(-) diff --git a/.travis/script.sh b/.travis/script.sh index dc7e22986..e87ed510b 100755 --- a/.travis/script.sh +++ b/.travis/script.sh @@ -11,7 +11,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then mkdir build cd build cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off - make -j2 + make -j16 else # For linux, we enable full package compilation #make diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index e59ebcaab..10c4b2bbe 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -510,13 +510,18 @@ static void ProcessSpiceModelBuffer(ezxml_t Node, ezxml_set_attr(Node, "topology", NULL); /*Find Tapered*/ + /* Set default values*/ + buffer->tapered_buf = 0; + buffer->tap_buf_level = 2; + buffer->f_per_stage = 4; + /* Parse XML */ Prop = my_strdup(FindProperty(Node, "tapered", read_buf_info)); if (NULL != Prop) { if (0 == strcmp(Prop,"on")) { buffer->tapered_buf = 1; /* Try to dig more properites ...*/ - buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 1); - buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4); + buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 2); + buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4); ezxml_set_attr(Node, "tap_drive_level", NULL); ezxml_set_attr(Node, "f_per_stage", NULL); } else if (0 == strcmp(FindProperty(Node,"tapered",TRUE),"off")) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp index 593da2889..a5378fcd9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_essential_gates.cpp @@ -84,7 +84,8 @@ void print_verilog_power_gated_invbuf_body(std::fstream& fp, * we wire the input to output */ if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) + && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { fp << "~"; } @@ -112,7 +113,7 @@ void print_verilog_invbuf_body(std::fstream& fp, print_verilog_comment(fp, std::string("----- Verilog codes of a regular inverter -----")); - fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " == 1'bz)? $random : "; + fp << "\tassign " << circuit_lib.port_lib_name(output_port) << " = (" << circuit_lib.port_lib_name(input_port) << " === 1'bz)? $random : "; /* Branch on the type of inverter/buffer: * 1. If this is an inverter or an tapered(multi-stage) buffer with odd number of stages, @@ -121,7 +122,8 @@ void print_verilog_invbuf_body(std::fstream& fp, * we wire the input to output */ if ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) - || ( (SPICE_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) + || ( (SPICE_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model)) + && (size_t(-1) != circuit_lib.buffer_num_levels(circuit_model)) && (1 == circuit_lib.buffer_num_levels(circuit_model) % 2 ) ) ) { fp << "~"; } @@ -208,7 +210,7 @@ void print_verilog_invbuf_module(std::fstream& fp, && ( SPICE_MODEL_BUF_BUF != circuit_lib.buffer_type(circuit_model)) ) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } @@ -272,7 +274,7 @@ void print_verilog_passgate_module(std::fstream& fp, default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid topology for circuit model (name=%s)!\n", - __FILE__, __LINE__, circuit_lib.model_name(circuit_model)); + __FILE__, __LINE__, circuit_lib.model_name(circuit_model).c_str()); exit(1); } @@ -556,7 +558,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, const std::string& submodule_dir, const CircuitLibrary& circuit_lib) { /* TODO: remove .bak when this part is completed and tested */ - std::string verilog_fname = submodule_dir + essentials_verilog_file_name + ".bak"; + std::string verilog_fname = submodule_dir + essentials_verilog_file_name; std::fstream fp; @@ -597,9 +599,7 @@ void print_verilog_submodule_essentials(const std::string& verilog_dir, fp.close(); /* Add fname to the linked list */ - /* TODO: enable this when this function is completed submodule_verilog_subckt_file_path_head = add_one_subckt_file_name_to_llist(submodule_verilog_subckt_file_path_head, verilog_fname.c_str()); - */ return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp index 39ba45e46..af28fc494 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodule_utils.cpp @@ -68,9 +68,9 @@ void print_verilog_submodule_timing(std::fstream& fp, fp << " => "; fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")"; fp << " = "; - fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE); + fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) / verilog_sim_timescale; fp << " , "; - fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_RISE) << ")"; + fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, SPICE_MODEL_DELAY_FALL) / verilog_sim_timescale << ")"; fp << ";" << std::endl; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index bc753174f..27a84e6d1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -4053,9 +4053,11 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 0. basic units: inverter, buffers and pass-gate logics, */ vpr_printf(TIO_MESSAGE_INFO, "Generating essential modules...\n"); + /* To be removed when testing passed dump_verilog_submodule_essentials(verilog_dir, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models); + */ print_verilog_submodule_essentials(std::string(verilog_dir), std::string(submodule_dir), Arch.spice->circuit_lib);