add utils for duplicate pins in grid module builder
This commit is contained in:
tangxifan
parent
895d5b5a0a
commit
59d579425e
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/********************************************************************
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* This file includes functions that are used to add duplicated
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* pins to each side of a grid
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*
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* These functions are located in this file, being separated from
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* the default functions in build_grid_module.cpp
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* This allows us to keep new features easy to be maintained.
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*
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* Please follow this rules when creating new features!
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*******************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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/* Headers from vpr library */
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#include "vpr_utils.h"
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#include "openfpga_naming.h"
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#include "openfpga_interconnect_types.h"
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#include "build_grid_module_utils.h"
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#include "build_grid_module_duplicated_pins.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* This function adds pb_type ports to top-level grid module with duplication
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* For each pin at each side, we create two pins which are short-wired
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* They are driven by the same pin, e.g., pinA in the child module
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* But in this top module, we will create two pins, each of which indicates
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* the physical location of pin.
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* Take the following example:
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* One is called pinA_upper which is located close to the top side of this grid
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* The other is called pinA_lower which is located close to the bottom side of this grid
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*
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* Similarly, we duplicate pins at TOP, RIGHT, BOTTOM and LEFT sides.
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* For LEFT side, upper and lower pins carry the indication in physical location as RIGHT side.
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* For TOP and BOTTOM side, upper pin is located close to the left side of a grid, while lower
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* pin is located close to the right side of a grid
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*
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* pinB_upper pinB_lower
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* ^ ^
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* | |
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* ---------------+
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* |--->pinA_upper
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* |
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* Grid |
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* |
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* |--->pinA_lower
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* ---------------+
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*******************************************************************/
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void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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t_physical_tile_type_ptr grid_type_descriptor,
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const e_side& border_side) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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* Otherwise, we will iterate all the 4 sides
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
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} else {
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grid_pin_sides = {TOP, RIGHT, BOTTOM, LEFT};
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}
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/* Create a map between pin class type and grid pin direction */
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std::map<e_pin_type, ModuleManager::e_module_port_type> pin_type2type_map;
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pin_type2type_map[RECEIVER] = ModuleManager::MODULE_INPUT_PORT;
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pin_type2type_map[DRIVER] = ModuleManager::MODULE_OUTPUT_PORT;
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/* Iterate over sides, height and pins */
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for (const e_side& side : grid_pin_sides) {
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for (int iwidth = 0; iwidth < grid_type_descriptor->width; ++iwidth) {
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for (int iheight = 0; iheight < grid_type_descriptor->height; ++iheight) {
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for (int ipin = 0; ipin < grid_type_descriptor->num_pins; ++ipin) {
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if (true != grid_type_descriptor->pinloc[iwidth][iheight][side][ipin]) {
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continue;
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}
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/* Reach here, it means this pin is on this side */
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int class_id = grid_type_descriptor->pin_class[ipin];
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e_pin_type pin_class_type = grid_type_descriptor->class_inf[class_id].type;
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/* Generate the pin name
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* For each RECEIVER PIN or DRIVER PIN for direct connection,
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* we do not duplicate in these cases */
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if ( (RECEIVER == pin_class_type)
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/* Xifan: I assume that each direct connection pin must have Fc=0. */
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|| ( (DRIVER == pin_class_type) && (0. == grid_type_descriptor->fc_specs[ipin].fc_value) ) ) {
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vtr::Point<size_t> dummy_coordinate;
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std::string port_name = generate_grid_port_name(dummy_coordinate, iwidth, iheight, side, ipin, false);
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BasicPort grid_port(port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_port, pin_type2type_map[pin_class_type]);
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} else {
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/* For each DRIVER pin, we create two copies.
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* One with a postfix of upper, indicating it is located on the upper part of a side
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* The other with a postfix of lower, indicating it is located on the lower part of a side
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*/
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VTR_ASSERT(DRIVER == pin_class_type);
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std::string upper_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, true);
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BasicPort grid_upper_port(upper_port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_upper_port, pin_type2type_map[pin_class_type]);
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std::string lower_port_name = generate_grid_duplicated_port_name(iwidth, iheight, side, ipin, false);
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BasicPort grid_lower_port(lower_port_name, 0, 0);
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/* Add the port to the module */
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module_manager.add_port(grid_module, grid_lower_port, pin_type2type_map[pin_class_type]);
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}
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}
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}
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}
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}
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}
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/********************************************************************
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* Add module nets to connect a port of child pb_module
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* to the duplicated pins of grid module
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* Note: This function SHOULD be ONLY applied to pb_graph output pins
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* of the child module.
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* For each such pin, we connect it to two outputs of the grid module
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* one is named after "upper", and the other is named after "lower"
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*******************************************************************/
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static
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void add_grid_module_net_connect_duplicated_pb_graph_pin(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_physical_tile_type_ptr grid_type_descriptor,
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t_pb_graph_pin* pb_graph_pin,
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const e_side& border_side,
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const e_pin2pin_interc_type& pin2pin_interc_type) {
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/* Make sure this is ONLY applied to output pins */
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VTR_ASSERT(OUTPUT2OUTPUT_INTERC == pin2pin_interc_type);
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/* Find the pin side for I/O grids*/
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std::vector<e_side> grid_pin_sides;
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/* For I/O grids, we care only one side
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* Otherwise, we will iterate all the 4 sides
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*/
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if (true == is_io_type(grid_type_descriptor)) {
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grid_pin_sides.push_back(find_grid_module_pin_side(grid_type_descriptor, border_side));
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} else {
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grid_pin_sides.push_back(TOP);
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grid_pin_sides.push_back(RIGHT);
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grid_pin_sides.push_back(BOTTOM);
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grid_pin_sides.push_back(LEFT);
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}
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/* num_pins/capacity = the number of pins that each type_descriptor has.
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* Capacity defines the number of type_descriptors in each grid
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* so the pin index at grid level = pin_index_in_type_descriptor
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* + type_descriptor_index_in_capacity * num_pins_per_type_descriptor
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*/
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size_t grid_pin_index = pb_graph_pin->pin_count_in_cluster
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+ child_instance * grid_type_descriptor->num_pins / grid_type_descriptor->capacity;
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int pin_width = grid_type_descriptor->pin_height_offset[grid_pin_index];
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int pin_height = grid_type_descriptor->pin_height_offset[grid_pin_index];
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for (const e_side& side : grid_pin_sides) {
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if (true != grid_type_descriptor->pinloc[pin_width][pin_height][side][grid_pin_index]) {
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continue;
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}
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/* Pins for direct connection are NOT duplicated.
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* Follow the traditional recipe when adding nets!
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* Xifan: I assume that each direct connection pin must have Fc=0.
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*/
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if (0. == grid_type_descriptor->fc_specs[grid_pin_index].fc_value) {
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the port in grid_module */
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vtr::Point<size_t> dummy_coordinate;
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std::string grid_port_name = generate_grid_port_name(dummy_coordinate, pin_width, pin_height, side, grid_pin_index, false);
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ModulePortId grid_module_port_id = module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_port_id));
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/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
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* if you need a change, please also change the port adding codes
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*/
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size_t grid_module_pin_id = 0;
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/* Find the port in child module */
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std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
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ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
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size_t child_module_pin_id = pb_graph_pin->pin_number;
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/* Add net sources and sinks:
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* For output-to-output connection, net_source is pb_graph_pin, while net_sink is grid pin
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*/
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module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_port_id, grid_module_pin_id);
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continue;
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}
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/* Reach here, it means this pin is on this side */
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/* Create a net to connect the grid pin to child module pin */
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ModuleNetId net = module_manager.create_module_net(grid_module);
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/* Find the upper port in grid_module */
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std::string grid_upper_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, true);
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ModulePortId grid_module_upper_port_id = module_manager.find_module_port(grid_module, grid_upper_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_upper_port_id));
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/* Find the lower port in grid_module */
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std::string grid_lower_port_name = generate_grid_duplicated_port_name(pin_width, pin_height, side, grid_pin_index, false);
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ModulePortId grid_module_lower_port_id = module_manager.find_module_port(grid_module, grid_lower_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module, grid_module_lower_port_id));
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/* Grid port always has only 1 pin, it is assumed when adding these ports to the module
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* if you need a change, please also change the port adding codes
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*/
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size_t grid_module_pin_id = 0;
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/* Find the port in child module */
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std::string child_module_port_name = generate_pb_type_port_name(pb_graph_pin->port);
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ModulePortId child_module_port_id = module_manager.find_module_port(child_module, child_module_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(child_module, child_module_port_id));
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size_t child_module_pin_id = pb_graph_pin->pin_number;
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/* Add net sources and sinks:
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* For output-to-output connection,
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* net_source is pb_graph_pin,
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* while net_sinks are grid upper pin and grid lower pin
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*/
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module_manager.add_module_net_source(grid_module, net, child_module, child_instance, child_module_port_id, child_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_upper_port_id, grid_module_pin_id);
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module_manager.add_module_net_sink(grid_module, net, grid_module, 0, grid_module_lower_port_id, grid_module_pin_id);
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}
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}
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/********************************************************************
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* Add module nets to connect a port of child pb_module
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* to the duplicated ports of grid module
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*******************************************************************/
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void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_physical_tile_type_ptr grid_type_descriptor,
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const e_side& border_side) {
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/* Ensure that we have a valid grid_type_descriptor */
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VTR_ASSERT(false == is_empty_type(grid_type_descriptor));
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for (t_logical_block_type_ptr lb_type : grid_type_descriptor->equivalent_sites) {
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t_pb_graph_node* top_pb_graph_node = lb_type->pb_graph_head;
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VTR_ASSERT(nullptr != top_pb_graph_node);
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for (int iport = 0; iport < top_pb_graph_node->num_input_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_input_pins[iport]; ++ipin) {
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add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->input_pins[iport][ipin]),
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border_side,
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INPUT2INPUT_INTERC);
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}
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}
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for (int iport = 0; iport < top_pb_graph_node->num_output_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_output_pins[iport]; ++ipin) {
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add_grid_module_net_connect_duplicated_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->output_pins[iport][ipin]),
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border_side,
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OUTPUT2OUTPUT_INTERC);
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}
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}
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for (int iport = 0; iport < top_pb_graph_node->num_clock_ports; ++iport) {
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for (int ipin = 0; ipin < top_pb_graph_node->num_clock_pins[iport]; ++ipin) {
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add_grid_module_net_connect_pb_graph_pin(module_manager, grid_module,
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child_module, child_instance,
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grid_type_descriptor,
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&(top_pb_graph_node->clock_pins[iport][ipin]),
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border_side,
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INPUT2INPUT_INTERC);
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}
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}
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}
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}
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} /* end namespace openfpga */
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@ -0,0 +1,32 @@
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#ifndef BUILD_GRID_MODULE_DUPLICATED_PINS_H
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#define BUILD_GRID_MODULE_DUPLICATED_PINS_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include "physical_types.h"
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#include "module_manager.h"
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#include "openfpga_side_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void add_grid_module_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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t_physical_tile_type_ptr grid_type_descriptor,
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const e_side& border_side);
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void add_grid_module_nets_connect_duplicated_pb_type_ports(ModuleManager& module_manager,
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const ModuleId& grid_module,
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const ModuleId& child_module,
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const size_t& child_instance,
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t_physical_tile_type_ptr grid_type_descriptor,
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const e_side& border_side);
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} /* end namespace openfpga */
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#endif
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