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Regression test succeeded

This commit is contained in:
Baudouin Chauviere 2019-07-09 09:18:06 -06:00
parent 25f5bc7792
commit 589f58b55e
3 changed files with 9 additions and 9 deletions
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4
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
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@ -336,8 +336,8 @@
<output_buffer exist="on" spice_model_name="INV1X"/> <output_buffer exist="on" spice_model_name="INV1X"/>
<pass_gate_logic spice_model_name="TGATEX1"/> <pass_gate_logic spice_model_name="TGATEX1"/>
<port type="input" prefix="D" size="1"/> <port type="input" prefix="D" size="1"/>
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/> <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/> <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
<port type="output" prefix="Q" size="1"/> <port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" /> <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
</spice_model> </spice_model>

4
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
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@ -1851,9 +1851,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
*/ */
bool is_explicit_full_name = true; bool is_explicit_full_name = true;
if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){ if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ /*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
is_explicit_full_name = false; is_explicit_full_name = false;
} }TEST*/
} }
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name); dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
/* Print I/O pads */ /* Print I/O pads */

10
vpr7_x2p/vpr/VerilogNetlists/io.v
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@ -3,14 +3,14 @@
//------ Author: Xifan TANG -----// //------ Author: Xifan TANG -----//
module iopad( module iopad(
//input zin, // Set output to be Z //input zin, // Set output to be Z
input dout, // Data output input outpad, // Data output
output din, // Data input output inpad, // Data input
inout pad, // bi-directional pad inout pad, // bi-directional pad
input direction // enable signal to control direction of iopad input en // enable signal to control direction of iopad
//input direction_inv // enable signal to control direction of iopad //input direction_inv // enable signal to control direction of iopad
); );
//----- when direction enabled, the signal is propagated from pad to din //----- when direction enabled, the signal is propagated from pad to din
assign din = direction ? pad : 1'bz; assign inpad = en ? pad : 1'bz;
//----- when direction is disabled, the signal is propagated from dout to pad //----- when direction is disabled, the signal is propagated from dout to pad
assign pad = direction ? 1'bz : dout; assign pad = en ? 1'bz : outpad;
endmodule endmodule