From 589f58b55ec6919c3c5da978ce9c375094692cad Mon Sep 17 00:00:00 2001
From: Baudouin Chauviere <baudouin.chauviere@utah.edu>
Date: Tue, 9 Jul 2019 09:18:06 -0600
Subject: [PATCH] Regression test succeeded

---
 .../arch/template/k6_N10_sram_chain_HC_template.xml    |  4 ++--
 vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c    |  4 ++--
 vpr7_x2p/vpr/VerilogNetlists/io.v                      | 10 +++++-----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
index 06e75d911..8dca26477 100644
--- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
+++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
@@ -336,8 +336,8 @@
          <output_buffer exist="on" spice_model_name="INV1X"/>
          <pass_gate_logic spice_model_name="TGATEX1"/>
          <port type="input" prefix="D" size="1"/>
-         <port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
-         <port type="input" prefix="Reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+         <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+         <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
          <port type="output" prefix="Q" size="1"/>
          <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
       </spice_model>
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
index 6fa1ad6da..25c162c48 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
@@ -1851,9 +1851,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
        */
       bool is_explicit_full_name = true;
       if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
-      if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
+      /*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
         is_explicit_full_name = false;
-      }
+      }TEST*/
       }
       dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
       /* Print I/O pads */
diff --git a/vpr7_x2p/vpr/VerilogNetlists/io.v b/vpr7_x2p/vpr/VerilogNetlists/io.v
index ab451b2b7..9fccdd23d 100644
--- a/vpr7_x2p/vpr/VerilogNetlists/io.v
+++ b/vpr7_x2p/vpr/VerilogNetlists/io.v
@@ -3,14 +3,14 @@
 //------ Author: Xifan TANG -----//
 module iopad(
 //input zin, // Set output to be Z
-input dout, // Data output
-output din, // Data input
+input outpad, // Data output
+output inpad, // Data input
 inout pad, // bi-directional pad
-input direction // enable signal to control direction of iopad
+input en // enable signal to control direction of iopad
 //input direction_inv // enable signal to control direction of iopad
 );
   //----- when direction enabled, the signal is propagated from pad to din
-  assign din = direction ? pad : 1'bz;
+  assign inpad = en ? pad : 1'bz;
   //----- when direction is disabled, the signal is propagated from dout to pad
-  assign pad = direction ? 1'bz : dout;
+  assign pad = en ? 1'bz : outpad;
 endmodule