diff --git a/docs/source/manual/file_formats/figures/tile_style_top_left.png b/docs/source/manual/file_formats/figures/tile_style_top_left.png
new file mode 100644
index 000000000..1e0f66575
Binary files /dev/null and b/docs/source/manual/file_formats/figures/tile_style_top_left.png differ
diff --git a/docs/source/manual/file_formats/index.rst b/docs/source/manual/file_formats/index.rst
index 1749fc68d..ac57bb1cc 100644
--- a/docs/source/manual/file_formats/index.rst
+++ b/docs/source/manual/file_formats/index.rst
@@ -37,3 +37,5 @@ OpenFPGA widely uses XML format for interchangable files
    clock_network
 
    io_naming_file
+
+   tile_config_tile
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
index fc552656c..add629dc6 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/setup_commands.rst
@@ -252,6 +252,14 @@ build_fabric
   .. option:: --compress_routing
 
     Enable compression on routing architecture modules. Strongly recommend this as it will minimize the number of routing modules to be outputted. It can reduce the netlist size significantly.
+
+  .. option:: --group_tile <string>
+
+    Group fine-grained programmable blocks, connection blocks and switch blocks into tiles. Once enabled, tiles will be added to the top-level module. Otherwise, the top-level module consists of programmable blocks, connection blocks and switch blocks. The tile style can be customized through a file. See details in :ref:`file_formats_tile_config_file`. 
+
+    .. warning:: This option does not support ``--duplicate_grid_pin``!
+   
+    .. warning:: This option requires ``--compress_routing`` to be enabled!
   
   .. option:: --duplicate_grid_pin