From 583c15131bfa991c73d327aa90d982b49869601f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 28 May 2020 21:33:44 -0600 Subject: [PATCH] change configuration latch to be triggered at negative edge; Frame-based fabric passed Modelsim verification but failed in iVerilog --- openfpga_flow/VerilogNetlists/config_latch.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v index 6cbe5657e..e177fe2e7 100644 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ b/openfpga_flow/VerilogNetlists/config_latch.v @@ -18,7 +18,7 @@ module config_latch ( reg q_reg; //-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset) begin +always @ ( negedge clk or posedge reset) begin if (reset) begin q_reg <= 1'b0; end else if (1'b1 == wl) begin