From 62bf0d0c5d2a9bccc655d0fad2ebe36abb84a304 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 16 Feb 2021 11:00:31 -0700 Subject: [PATCH] [Test] Move quicklogic regresssion tests to a dedicated CI run --- .github/workflows/build.yml | 2 ++ .github/workflows/quicklogic_reg_test.sh | 12 ++++++++++++ 2 files changed, 14 insertions(+) create mode 100755 .github/workflows/quicklogic_reg_test.sh diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 1326b2fd3..11616f4f0 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -209,6 +209,7 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: quicklogic_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 @@ -253,6 +254,7 @@ jobs: - name: fpga_bitstream_reg_test - name: fpga_sdc_reg_test - name: fpga_spice_reg_test + - name: quicklogic_reg_test steps: - name: Checkout OpenFPGA repo uses: actions/checkout@v2 diff --git a/.github/workflows/quicklogic_reg_test.sh b/.github/workflows/quicklogic_reg_test.sh new file mode 100755 index 000000000..32f7f3650 --- /dev/null +++ b/.github/workflows/quicklogic_reg_test.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +set -e +source openfpga.sh +PYTHON_EXEC=python3.8 +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "QuickLogic regression tests"; + +echo -e "Testing yosys flow using custom ys script for running quicklogic device"; +run-task quicklogic_tests/flow_test --debug --show_thread_logs