bug fixing for rectangle FPGA sizes
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edfe3144c3
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@ -986,7 +986,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
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/* Get X-channel CB coordinator */
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/* Get X-channel CB coordinator */
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const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
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const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX);
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/* X - channels [1...nx][0..ny]*/
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/* X - channels [1...nx][0..ny]*/
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if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x()))
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if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y()))
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&&(true == rr_gsb.is_cb_exist(CHANX))) {
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&&(true == rr_gsb.is_cb_exist(CHANX))) {
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX);
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}
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}
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@ -994,7 +994,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or
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/* Get X-channel CB coordinator */
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/* Get X-channel CB coordinator */
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const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
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const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY);
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/* Y - channels [1...ny][0..nx]*/
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/* Y - channels [1...ny][0..nx]*/
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if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x()))
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if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y()))
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&&(true == rr_gsb.is_cb_exist(CHANY))) {
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&&(true == rr_gsb.is_cb_exist(CHANY))) {
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);
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dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY);
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}
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}
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