diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
index efa77aaf7..c9a360489 100644
--- a/openfpga/src/base/openfpga_verilog.cpp
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -26,8 +26,6 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_output_dir = cmd.option("file");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
   CommandOptionId opt_include_timing = cmd.option("include_timing");
-  CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
-  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
@@ -38,8 +36,6 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
   options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
   options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
-  options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
-  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
@@ -73,6 +69,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_print_preconfig_top_testbench = cmd.option("print_preconfig_top_testbench");
   CommandOptionId opt_print_simulation_ini = cmd.option("print_simulation_ini");
   CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
+  CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
+  CommandOptionId opt_support_icarus_simulator = cmd.option("support_icarus_simulator");
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   /* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@@ -88,6 +86,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
   options.set_print_top_testbench(cmd_context.option_enable(cmd, opt_print_top_testbench));
   options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
   options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
+  options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
+  options.set_support_icarus_simulator(cmd_context.option_enable(cmd, opt_support_icarus_simulator));
   options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
   
   fpga_verilog_testbench(openfpga_ctx.module_graph(),
diff --git a/openfpga/src/base/openfpga_verilog_command.cpp b/openfpga/src/base/openfpga_verilog_command.cpp
index 116d2842c..8eb8d83df 100644
--- a/openfpga/src/base/openfpga_verilog_command.cpp
+++ b/openfpga/src/base/openfpga_verilog_command.cpp
@@ -33,12 +33,6 @@ ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<Openfpg
   /* Add an option '--include_timing' */
   shell_cmd.add_option("include_timing", false, "Enable timing annotation in Verilog netlists");
 
-  /* Add an option '--include_signal_init' */
-  shell_cmd.add_option("include_signal_init", false, "Initialize all the signals in Verilog netlists");
-
-  /* Add an option '--support_icarus_simulator' */
-  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog netlists to support icarus simulator");
-
   /* Add an option '--print_user_defined_template' */
   shell_cmd.add_option("print_user_defined_template", false, "Generate a template Verilog files for user-defined circuit models");
 
@@ -99,6 +93,12 @@ ShellCommandId add_openfpga_write_verilog_testbench_command(openfpga::Shell<Open
   /* Add an option '--explicit_port_mapping' */
   shell_cmd.add_option("explicit_port_mapping", false, "Use explicit port mapping in Verilog netlists");
 
+  /* Add an option '--include_signal_init' */
+  shell_cmd.add_option("include_signal_init", false, "Initialize all the signals in Verilog testbenches");
+
+  /* Add an option '--support_icarus_simulator' */
+  shell_cmd.add_option("support_icarus_simulator", false, "Fine-tune Verilog testbenches to support icarus simulator");
+
   /* Add an option '--verbose' */
   shell_cmd.add_option("verbose", false, "Enable verbose output");
   
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
index 3bf851659..ab6e9366c 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.cpp
@@ -13,8 +13,6 @@ namespace openfpga {
  *************************************************/
 FabricVerilogOption::FabricVerilogOption() {
   output_directory_.clear();
-  support_icarus_simulator_ = false;
-  include_signal_init_ = false;
   include_timing_ = false;
   explicit_port_mapping_ = false;
   compress_routing_ = false;
@@ -29,18 +27,10 @@ std::string FabricVerilogOption::output_directory() const {
   return output_directory_;
 }
 
-bool FabricVerilogOption::support_icarus_simulator() const {
-  return support_icarus_simulator_;
-}
-
 bool FabricVerilogOption::include_timing() const {
   return include_timing_;
 }
 
-bool FabricVerilogOption::include_signal_init() const {
-  return include_signal_init_;
-}
-
 bool FabricVerilogOption::explicit_port_mapping() const {
   return explicit_port_mapping_;
 }
@@ -64,18 +54,10 @@ void FabricVerilogOption::set_output_directory(const std::string& output_dir) {
   output_directory_ = output_dir;
 }
 
-void FabricVerilogOption::set_support_icarus_simulator(const bool& enabled) {
-  support_icarus_simulator_ = enabled;
-}
-
 void FabricVerilogOption::set_include_timing(const bool& enabled) {
   include_timing_ = enabled;
 }
 
-void FabricVerilogOption::set_include_signal_init(const bool& enabled) {
-  include_signal_init_ = enabled;
-}
-
 void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
   explicit_port_mapping_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/fabric_verilog_options.h b/openfpga/src/fpga_verilog/fabric_verilog_options.h
index 22c9b51c5..207f77fe8 100644
--- a/openfpga/src/fpga_verilog/fabric_verilog_options.h
+++ b/openfpga/src/fpga_verilog/fabric_verilog_options.h
@@ -18,26 +18,20 @@ class FabricVerilogOption {
     FabricVerilogOption();
   public: /* Public accessors */
     std::string output_directory() const;
-    bool support_icarus_simulator() const;
     bool include_timing() const;
-    bool include_signal_init() const;
     bool explicit_port_mapping() const;
     bool compress_routing() const;
     bool print_user_defined_template() const;
     bool verbose_output() const;
   public: /* Public mutators */
     void set_output_directory(const std::string& output_dir);
-    void set_support_icarus_simulator(const bool& enabled);
     void set_include_timing(const bool& enabled);
-    void set_include_signal_init(const bool& enabled);
     void set_explicit_port_mapping(const bool& enabled);
     void set_compress_routing(const bool& enabled);
     void set_print_user_defined_template(const bool& enabled);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
-    bool support_icarus_simulator_;
-    bool include_signal_init_;
     bool include_timing_;
     bool explicit_port_mapping_;
     bool compress_routing_;
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 29ecab1f7..e012c32e6 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -169,7 +169,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
   /* Create directories */
   create_directory(src_dir_path);
 
-  /* TODO: check if this works here. This function was in fabric generator */
+  /* Output preprocessing flags for HDL simulations */
   print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
                                                options);
 
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 612c65557..b0bacad37 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -184,18 +184,6 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
     fp << std::endl;
   } 
 
-  /* To enable timing */
-  if (true == fabric_verilog_opts.include_signal_init()) {
-    print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
-    fp << std::endl;
-  } 
-
-  /* To enable functional verfication with Icarus */
-  if (true == fabric_verilog_opts.support_icarus_simulator()) {
-    print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
-    fp << std::endl;
-  } 
-
   /* Close the file stream */
   fp.close();
 }
@@ -218,6 +206,18 @@ void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
   /* Print the title */
   print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
 
+  /* To enable signal initialization */
+  if (true == verilog_testbench_opts.include_signal_init()) {
+    print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
+    fp << std::endl;
+  } 
+
+  /* To enable functional verfication with Icarus */
+  if (true == verilog_testbench_opts.support_icarus_simulator()) {
+    print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
+    fp << std::endl;
+  } 
+
   /* To enable manualy checked simulation */
   if (true == verilog_testbench_opts.print_top_testbench()) {
     print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
index 8c009f823..b39adef43 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.cpp
@@ -21,6 +21,8 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
   print_top_testbench_ = false;
   simulation_ini_path_.clear();
   explicit_port_mapping_ = false;
+  support_icarus_simulator_ = false;
+  include_signal_init_ = false;
   verbose_output_ = false;
 }
 
@@ -67,6 +69,14 @@ bool VerilogTestbenchOption::explicit_port_mapping() const {
   return explicit_port_mapping_;
 }
 
+bool VerilogTestbenchOption::include_signal_init() const {
+  return include_signal_init_;
+}
+
+bool VerilogTestbenchOption::support_icarus_simulator() const {
+  return support_icarus_simulator_;
+}
+
 bool VerilogTestbenchOption::verbose_output() const {
   return verbose_output_;
 }
@@ -123,6 +133,14 @@ void VerilogTestbenchOption::set_explicit_port_mapping(const bool& enabled) {
   explicit_port_mapping_ = enabled;
 }
 
+void VerilogTestbenchOption::set_include_signal_init(const bool& enabled) {
+  include_signal_init_ = enabled;
+}
+
+void VerilogTestbenchOption::set_support_icarus_simulator(const bool& enabled) {
+  support_icarus_simulator_ = enabled;
+}
+
 void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
   verbose_output_ = enabled;
 }
diff --git a/openfpga/src/fpga_verilog/verilog_testbench_options.h b/openfpga/src/fpga_verilog/verilog_testbench_options.h
index 72a64f494..492740f8e 100644
--- a/openfpga/src/fpga_verilog/verilog_testbench_options.h
+++ b/openfpga/src/fpga_verilog/verilog_testbench_options.h
@@ -32,6 +32,8 @@ class VerilogTestbenchOption {
     bool print_simulation_ini() const;
     std::string simulation_ini_path() const;
     bool explicit_port_mapping() const;
+    bool include_signal_init() const;
+    bool support_icarus_simulator() const;
     bool verbose_output() const;
   public: /* Public validator */
     bool validate() const;
@@ -54,6 +56,8 @@ class VerilogTestbenchOption {
     void set_print_top_testbench(const bool& enabled);
     void set_print_simulation_ini(const std::string& simulation_ini_path);
     void set_explicit_port_mapping(const bool& enabled);
+    void set_include_signal_init(const bool& enabled);
+    void set_support_icarus_simulator(const bool& enabled);
     void set_verbose_output(const bool& enabled);
   private: /* Internal Data */
     std::string output_directory_;
@@ -66,6 +70,8 @@ class VerilogTestbenchOption {
     /* Print simulation ini is enabled only when the path is not empty */
     std::string simulation_ini_path_;
     bool explicit_port_mapping_;
+    bool support_icarus_simulator_;
+    bool include_signal_init_;
     bool verbose_output_;
 };