From 5794561f7bb5ff27ac37d6d9f55bbf8291f12681 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 14 Feb 2022 10:39:27 -0800 Subject: [PATCH] [FPGA-Verilog] Now shared input wire/register has a postfix in full testbench --- .../fpga_verilog/verilog_formal_random_top_testbench.cpp | 2 ++ openfpga/src/fpga_verilog/verilog_testbench_utils.cpp | 8 +++++--- openfpga/src/fpga_verilog/verilog_testbench_utils.h | 2 ++ openfpga/src/fpga_verilog/verilog_top_testbench.cpp | 6 +++++- .../src/fpga_verilog/verilog_top_testbench_constants.h | 1 + 5 files changed, 15 insertions(+), 4 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index d1c79f4fb..7ad5e2c32 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -81,6 +81,7 @@ void print_verilog_top_random_testbench_ports(std::fstream& fp, print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation, clock_port_names, + std::string(), std::string(BENCHMARK_PORT_POSTFIX), std::string(FPGA_PORT_POSTFIX), std::string(CHECKFLAG_PORT_POSTFIX), @@ -345,6 +346,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, global_ports, pin_constraints, clock_port_names, + std::string(), std::string(CHECKFLAG_PORT_POSTFIX), clock_ports, options.no_self_checking()); diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index 40a863c6e..26ed89348 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -580,6 +580,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::vector& clock_port_names, + const std::string& input_port_postfix, const std::string& check_flag_port_postfix, const std::vector& clock_ports, const bool& no_self_checking) { @@ -617,7 +618,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name << " <= 1'b0;" << std::endl; + fp << "\t\t" << block_name + input_port_postfix << " <= 1'b0;" << std::endl; } } @@ -686,7 +687,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, /* TODO: find the clock inputs will be initialized later */ if (AtomBlockType::INPAD == atom_ctx.nlist.block_type(atom_blk)) { - fp << "\t\t" << block_name << " <= $random;" << std::endl; + fp << "\t\t" << block_name + input_port_postfix << " <= $random;" << std::endl; } } @@ -709,6 +710,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, @@ -736,7 +738,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, } /* Each logical block assumes a single-width port */ - BasicPort input_port(block_name, 1); + BasicPort input_port(block_name + shared_input_port_postfix, 1); fp << "\t" << generate_verilog_port(VERILOG_PORT_REG, input_port) << ";" << std::endl; } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index 84b3750bb..a7c8789d7 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -89,6 +89,7 @@ void print_verilog_testbench_random_stimuli(std::fstream& fp, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, const std::vector& clock_port_names, + const std::string& input_port_postfix, const std::string& check_flag_port_postfix, const std::vector& clock_ports, const bool& no_self_checking); @@ -97,6 +98,7 @@ void print_verilog_testbench_shared_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, + const std::string& shared_input_port_postfix, const std::string& benchmark_output_port_postfix, const std::string& fpga_output_port_postfix, const std::string& check_flag_port_postfix, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 0ec778222..7daff2799 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -800,6 +800,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation, clock_port_names, + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), @@ -1810,6 +1811,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, const ModuleManager& module_manager, const FabricGlobalPortInfo& global_ports, const PinConstraints& pin_constraints, + const std::string& port_name_postfix, const std::vector& clock_port_names) { valid_file_stream(fp); @@ -1842,7 +1844,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); /* Connect stimuli to greset with an optional inversion, depending on the default value */ - BasicPort reset_port(block_name, 1); + BasicPort reset_port(block_name + port_name_postfix, 1); print_verilog_wire_connection(fp, reset_port, BasicPort(TOP_TB_RESET_PORT_NAME, 1), 1 == initial_value); @@ -2094,6 +2096,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, module_manager, global_ports, pin_constraints, + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), clock_port_names); print_verilog_testbench_random_stimuli(fp, atom_ctx, netlist_annotation, @@ -2101,6 +2104,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, global_ports, pin_constraints, clock_port_names, + std::string(TOP_TESTBENCH_SHARED_INPUT_POSTFIX), std::string(TOP_TESTBENCH_CHECKFLAG_PORT_POSTFIX), std::vector(1, BasicPort(std::string(TOP_TB_OP_CLOCK_PORT_NAME), 1)), options.no_self_checking()); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench_constants.h b/openfpga/src/fpga_verilog/verilog_top_testbench_constants.h index 31c251ee4..8da645cf5 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench_constants.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench_constants.h @@ -6,6 +6,7 @@ namespace openfpga { constexpr char* TOP_TESTBENCH_REFERENCE_INSTANCE_NAME = "REF_DUT"; constexpr char* TOP_TESTBENCH_FPGA_INSTANCE_NAME = "FPGA_DUT"; +constexpr char* TOP_TESTBENCH_SHARED_INPUT_POSTFIX = "_shared_input"; constexpr char* TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX = "_benchmark"; constexpr char* TOP_TESTBENCH_FPGA_OUTPUT_POSTFIX = "_fpga";