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Update eda_flow.rst 

Completed with FPGA-Verilog/Bitstream and corrected few errors
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EDA flow EDA flow
======== ========
As illustrated in :numref:`fig_eda_flow` , FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis needs the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in Section V). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results, when enabled by command-line options. (See Section IV for details about command-line options.) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See Section VII for guidelines in customize your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e. HSPICE, can be called to conduct power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See Section VIII). As illustrated in :numref:`fig_eda_flow` , FPGA-SPICE creates a modified VTR flow. All the input files for VPR do not need modifications except the architecture description XML. As simulation-based power analysis needs the transistor-level netlists, we extend the architecture description language to support transistor-level modeling (See details in "Tools Guide>Extended Architecture Description Language"). FPGA-SPICE, embedded in VPR, outputs the SPICE netlists and testbenches according to placement and routing results, when enabled by command-line options. (See each "FPGA-*Branch*" about command-line options available) Besides automatically generating all the SPICE netlists, FPGA-SPICE supports user-defined SPICE netlists for modules. We believe the support on user-defined SPICE netlists allows FPGA-SPICE to be general enough to support novel circuit designs and even technologies. (See "FPGA-SPICE... > Create Customized SPICE Modules" for guidelines in customize your FPGA-SPICE compatible SPICE netlists.) With the dumped SPICE netlists and testbenches, a SPICE simulator, i.e. HSPICE, can be called to conduct power analysis. FPGA-SPICE automatically generates a shell script, which brings convenience for users to run all the simulations (See "FPGA-SPICE... > Run SPICE simulation").
.. _fig_eda_flow: .. _fig_eda_flow:
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:scale: 50% :scale: 50%
:alt: map to buried treasure :alt: map to buried treasure
Detailed EDA flows based on FPGA-SPICE/Verilog/Bitstream in the purpose of : (a) prototyping and area analysis (b) power analysis; and (c) functionality verificaiton. Detailed EDA flows based on FPGA-SPICE/Verilog/Bitstream in the purpose of : (a) architecture of the output of FPGA-SPICE (b) functionality verification; (c) prototyping and area analysis and (d) power analysis. *TBD:change for Yosys*
FPGA-Verilog is the part of the flow in charge of the Verilog and the semi-custom design flow. In our case, we use Cadence Innovus. The goal is to get the full-FPGA layout to complete the analysis provided by FPGA-SPICE. By having the layout, we can get an area analysis on one hand and have new informations concerning the power analysis. For instance, having the layout allows the user to have new informations on the circuit such as the parasitics.
FPGA-Bitstream is the part of the flow in charge of the functional verification of the produced FPGA. Testbenches are generated by FPGA-SPICE and are combined to the full FPGA fabric in Modelsim. A bitstream is generated at the same time as the testbenches. This bitstream configures the FPGA with the functionality given by the user to VPR at the beginning of the flow. First we configure the FPGA with the bitstream and then waveforms are sent onto the I/O pads to check the functionality.
How to compile How to compile
============== ==============
Running the Makefile in the released package can compile all the source codes. Running the Makefile in the root of the released package can compile all the source codes.
The released package includes a version of VPR with FPGA-SPICE support, ABC with black box support and Activity Estimator. The released package includes a version of VPR with FPGA-SPICE support, Yosys and ACE2.