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This commit is contained in:
Baudouin Chauviere 2018-10-09 15:10:07 -06:00
parent bee23b6cb1
commit 5734b56502
1 changed files with 3 additions and 3 deletions
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6
examples/Examples_README.md
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@ -6,7 +6,7 @@ The goal of this example is just to make a first step into the software. The .bl
The .xml is currently on <layout auto="1.0"/> which means that the size depends on the .blif. Since the .blif is
almost empty, only 1 CLB will be generated.
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" width="60%">
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_1.png" alt="Example_1_FPGA" class="center" width="60%">
Schematic of the FPGA generated during example_1.
The CLB integrates a 4-inputs LUT, a FF and a MUX.
@ -52,7 +52,7 @@ Example_2's goal is to introduce the slices, the interconnections which can be g
In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry.
There is a feedback-loop from the output of the slices to the input MUXs
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png" alt="Example_2_CLB" width="60%">
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_the_CLB.png" alt="Example_2_CLB" class="center" width="60%">
Schematic showing the CLB generated in this example.
@ -70,7 +70,7 @@ Schematic showing the CLB generated in this example.
</complete>
```
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png" alt="Example_2_FPGA" width="60%">
<img src="https://github.com/LNIS-Projects/OpenFPGA/blob/master/examples/figures/example_2_3x3.png" alt="Example_2_FPGA" class="center" width="60%">