diff --git a/openfpga_flow/VerilogNetlists/dpram_32x1024.v b/openfpga_flow/VerilogNetlists/dpram.v
similarity index 100%
rename from openfpga_flow/VerilogNetlists/dpram_32x1024.v
rename to openfpga_flow/VerilogNetlists/dpram.v
diff --git a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
index 10cd18ddd..103152e31 100644
--- a/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
+++ b/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
@@ -146,7 +146,7 @@
-
+
@@ -163,8 +163,8 @@
-
-
+
+
@@ -344,14 +344,14 @@
-
+
-
-
+
+
@@ -386,17 +386,17 @@
-
+
-
+
-
+
@@ -421,7 +421,7 @@
-
+
@@ -613,7 +613,7 @@
-
+
@@ -631,7 +631,7 @@
-
+
@@ -674,13 +674,13 @@
-
-
+
memory_dp.d_in
- memory_dp.clk memory_dp.wen memory_dp.waddr
+ memory_dp.clk memory_dp.wen memory_dp.waddr
memory_dp.d_out
memory_dp.ren memory_dp.raddr
-
+
diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act
new file mode 100644
index 000000000..d8c59ec70
--- /dev/null
+++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act
@@ -0,0 +1,95 @@
+clk 0.5 0.2
+wen 0.5 0.2
+wen_st0 0.5 0.2
+wen_st1 0.5 0.2
+ren 0.5 0.2
+raddr_0_ 0.5 0.2
+raddr_1_ 0.5 0.2
+raddr_2_ 0.5 0.2
+raddr_3_ 0.5 0.2
+raddr_4_ 0.5 0.2
+raddr_5_ 0.5 0.2
+waddr_0_ 0.5 0.2
+waddr_1_ 0.5 0.2
+waddr_2_ 0.5 0.2
+waddr_3_ 0.5 0.2
+waddr_4_ 0.5 0.2
+waddr_5_ 0.5 0.2
+waddr_st0_0_ 0.5 0.2
+waddr_st0_1_ 0.5 0.2
+waddr_st0_2_ 0.5 0.2
+waddr_st0_3_ 0.5 0.2
+waddr_st0_4_ 0.5 0.2
+waddr_st0_5_ 0.5 0.2
+waddr_st1_0_ 0.5 0.2
+waddr_st1_1_ 0.5 0.2
+waddr_st1_2_ 0.5 0.2
+waddr_st1_3_ 0.5 0.2
+waddr_st1_4_ 0.5 0.2
+waddr_st1_5_ 0.5 0.2
+a_0_ 0.5 0.2
+a_1_ 0.5 0.2
+a_2_ 0.5 0.2
+a_3_ 0.5 0.2
+a_4_ 0.5 0.2
+a_5_ 0.5 0.2
+a_6_ 0.5 0.2
+a_st0_0_ 0.5 0.2
+a_st0_1_ 0.5 0.2
+a_st0_2_ 0.5 0.2
+a_st0_3_ 0.5 0.2
+a_st0_4_ 0.5 0.2
+a_st0_5_ 0.5 0.2
+a_st0_6_ 0.5 0.2
+a_st1_0_ 0.5 0.2
+a_st1_1_ 0.5 0.2
+a_st1_2_ 0.5 0.2
+a_st1_3_ 0.5 0.2
+a_st1_4_ 0.5 0.2
+a_st1_5_ 0.5 0.2
+a_st1_6_ 0.5 0.2
+b_0_ 0.5 0.2
+b_1_ 0.5 0.2
+b_2_ 0.5 0.2
+b_3_ 0.5 0.2
+b_4_ 0.5 0.2
+b_5_ 0.5 0.2
+b_6_ 0.5 0.2
+b_st0_0_ 0.5 0.2
+b_st0_1_ 0.5 0.2
+b_st0_2_ 0.5 0.2
+b_st0_3_ 0.5 0.2
+b_st0_4_ 0.5 0.2
+b_st0_5_ 0.5 0.2
+b_st0_6_ 0.5 0.2
+b_st1_0_ 0.5 0.2
+b_st1_1_ 0.5 0.2
+b_st1_2_ 0.5 0.2
+b_st1_3_ 0.5 0.2
+b_st1_4_ 0.5 0.2
+b_st1_5_ 0.5 0.2
+b_st1_6_ 0.5 0.2
+q_0_ 0.5 0.2
+q_1_ 0.5 0.2
+q_2_ 0.5 0.2
+q_3_ 0.5 0.2
+q_4_ 0.5 0.2
+q_5_ 0.5 0.2
+q_6_ 0.5 0.2
+q_7_ 0.5 0.2
+AplusB_0_ 0.5 0.2
+AplusB_1_ 0.5 0.2
+AplusB_2_ 0.5 0.2
+AplusB_3_ 0.5 0.2
+AplusB_4_ 0.5 0.2
+AplusB_5_ 0.5 0.2
+AplusB_6_ 0.5 0.2
+AplusB_7_ 0.5 0.2
+cint01 0.5 0.2
+cint02 0.5 0.2
+cint03 0.5 0.2
+cint04 0.5 0.2
+cint05 0.5 0.2
+cint06 0.5 0.2
+cint07 0.5 0.2
+zero00 0 0
diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif
new file mode 100644
index 000000000..4ec6b2a99
--- /dev/null
+++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif
@@ -0,0 +1,126 @@
+# Benchmark pipelined_32b_adder
+.model pipelined_32b_adder
+.inputs clk wen ren raddr_0_ raddr_1_ raddr_2_ raddr_3_ raddr_4_ raddr_5_ waddr_0_ waddr_1_ waddr_2_ waddr_3_ waddr_4_ waddr_5_ a_0_ a_1_ a_2_ a_3_ a_4_ a_5_ a_6_ b_0_ b_1_ b_2_ b_3_ b_4_ b_5_ b_6_
+.outputs q_0_ q_1_ q_2_ q_3_ q_4_ q_5_ q_6_ q_7_
+
+# Start pipeline
+# Pipeline a
+.subckt shift D=a_0_ clk=clk Q=a_st0_0_
+.subckt shift D=a_st0_0_ clk=clk Q=a_st1_0_
+.subckt shift D=a_1_ clk=clk Q=a_st0_1_
+.subckt shift D=a_st0_1_ clk=clk Q=a_st1_1_
+.subckt shift D=a_2_ clk=clk Q=a_st0_2_
+.subckt shift D=a_st0_2_ clk=clk Q=a_st1_2_
+.subckt shift D=a_3_ clk=clk Q=a_st0_3_
+.subckt shift D=a_st0_3_ clk=clk Q=a_st1_3_
+.subckt shift D=a_4_ clk=clk Q=a_st0_4_
+.subckt shift D=a_st0_4_ clk=clk Q=a_st1_4_
+.subckt shift D=a_5_ clk=clk Q=a_st0_5_
+.subckt shift D=a_st0_5_ clk=clk Q=a_st1_5_
+.subckt shift D=a_6_ clk=clk Q=a_st0_6_
+.subckt shift D=a_st0_6_ clk=clk Q=a_st1_6_
+
+# Pipeline b
+.subckt shift D=b_0_ clk=clk Q=b_st0_0_
+.subckt shift D=b_st0_0_ clk=clk Q=b_st1_0_
+.subckt shift D=b_1_ clk=clk Q=b_st0_1_
+.subckt shift D=b_st0_1_ clk=clk Q=b_st1_1_
+.subckt shift D=b_2_ clk=clk Q=b_st0_2_
+.subckt shift D=b_st0_2_ clk=clk Q=b_st1_2_
+.subckt shift D=b_3_ clk=clk Q=b_st0_3_
+.subckt shift D=b_st0_3_ clk=clk Q=b_st1_3_
+.subckt shift D=b_4_ clk=clk Q=b_st0_4_
+.subckt shift D=b_st0_4_ clk=clk Q=b_st1_4_
+.subckt shift D=b_5_ clk=clk Q=b_st0_5_
+.subckt shift D=b_st0_5_ clk=clk Q=b_st1_5_
+.subckt shift D=b_6_ clk=clk Q=b_st0_6_
+.subckt shift D=b_st0_6_ clk=clk Q=b_st1_6_
+
+# Pipeline waddr
+.subckt shift D=waddr_0_ clk=clk Q=waddr_st0_0_
+.subckt shift D=waddr_st0_0_ clk=clk Q=waddr_st1_0_
+.subckt shift D=waddr_1_ clk=clk Q=waddr_st0_1_
+.subckt shift D=waddr_st0_1_ clk=clk Q=waddr_st1_1_
+.subckt shift D=waddr_2_ clk=clk Q=waddr_st0_2_
+.subckt shift D=waddr_st0_2_ clk=clk Q=waddr_st1_2_
+.subckt shift D=waddr_3_ clk=clk Q=waddr_st0_3_
+.subckt shift D=waddr_st0_3_ clk=clk Q=waddr_st1_3_
+.subckt shift D=waddr_4_ clk=clk Q=waddr_st0_4_
+.subckt shift D=waddr_st0_4_ clk=clk Q=waddr_st1_4_
+.subckt shift D=waddr_5_ clk=clk Q=waddr_st0_5_
+.subckt shift D=waddr_st0_5_ clk=clk Q=waddr_st1_5_
+# Pipeline wen
+.subckt shift D=wen clk=clk Q=wen_st0
+.subckt shift D=wen_st0 clk=clk Q=wen_st1
+# End pipeline
+
+# Start adder
+.subckt adder a=a_st1_0_ b=b_st1_0_ cin=zero00 cout=cint01 sumout=AplusB_0_
+.subckt adder a=a_st1_1_ b=b_st1_1_ cin=cint01 cout=cint02 sumout=AplusB_1_
+.subckt adder a=a_st1_2_ b=b_st1_2_ cin=cint02 cout=cint03 sumout=AplusB_2_
+.subckt adder a=a_st1_3_ b=b_st1_3_ cin=cint03 cout=cint04 sumout=AplusB_3_
+.subckt adder a=a_st1_4_ b=b_st1_4_ cin=cint04 cout=cint05 sumout=AplusB_4_
+.subckt adder a=a_st1_5_ b=b_st1_5_ cin=cint05 cout=cint06 sumout=AplusB_5_
+.subckt adder a=a_st1_6_ b=b_st1_6_ cin=cint06 cout=cint07 sumout=AplusB_6_
+.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB_7_
+# End adder
+
+# Start DPRAM
+.subckt dual_port_ram_32x1024 clk=clk wen=wen_st1 ren=ren \
+waddr[0]=waddr_st1_0_ waddr[1]=waddr_st1_1_ waddr[2]=waddr_st1_2_ waddr[3]=waddr_st1_3_ waddr[4]=waddr_st1_4_ \
+waddr[5]=waddr_st1_5_ waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 \
+raddr[0]=raddr_0_ raddr[1]=raddr_1_ raddr[2]=raddr_2_ raddr[3]=raddr_3_ raddr[4]=raddr_4_ raddr[5]=raddr_5_ \
+raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 \
+d_in[0]=AplusB_0_ d_in[1]=AplusB_1_ d_in[2]=AplusB_2_ d_in[3]=AplusB_3_ d_in[4]=AplusB_4_ d_in[5]=AplusB_5_ \
+d_in[6]=AplusB_6_ d_in[7]=AplusB_7_ d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
+d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
+d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
+d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
+d_in[30]=zero00 d_in[31]=zero00 \
+d_out[0]=q_0_ d_out[1]=q_1_ d_out[2]=q_2_ d_out[3]=q_3_ d_out[4]=q_4_ d_out[5]=q_5_ \
+d_out[6]=q_6_ d_out[7]=q_7_ d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
+d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
+d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
+d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
+d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn
+# End DPRAM
+
+# Start global variable
+.names zero00
+0
+# End global variable
+
+
+.end
+
+# Start blackbox definition
+.model dual_port_ram_32x1024
+.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
+ waddr[6] waddr[7] waddr[8] raddr[0] raddr[1] raddr[2] \
+ raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] \
+ d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
+ d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
+ d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
+ d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31]
+.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
+ d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
+ d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
+ d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
+ d_out[28] d_out[29] d_out[30] d_out[31]
+.blackbox
+.end
+
+
+.model adder
+.inputs a b cin
+.outputs cout sumout
+.blackbox
+.end
+
+
+.model shift
+.inputs D clk
+.outputs Q
+.blackbox
+.end
+# End blackbox definition
diff --git a/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v
new file mode 100644
index 000000000..549ef735a
--- /dev/null
+++ b/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v
@@ -0,0 +1,99 @@
+// //
+// ERI summit demo-benchmark //
+// pipelined_8b_adder.v //
+// by Aurelien //
+// //
+/////////////////////////////////////
+//-----------------------------------------------------
+// Design Name : pipelined_8bit_adder
+// File Name : pipelined_8bit_adder.v
+// Function : Pipelined 8-bit adders, whose sum and carry outputs
+// are cached in a memory
+// Coder : Aurelien Alacchi
+//-----------------------------------------------------
+
+`timescale 1 ns/ 1 ps
+
+// To match the port definition in BLIF format, so that we can do verification
+// Each input/output bus is expanded here.
+// In future, we should be able to support buses in verification!
+
+module pipelined_8bit_adder(
+ input clk,
+ input ren,
+ input wen,
+ input raddr_0_,
+ input raddr_1_,
+ input raddr_2_,
+ input raddr_3_,
+ input raddr_4_,
+ input raddr_5_,
+ input waddr_0_,
+ input waddr_1_,
+ input waddr_2_,
+ input waddr_3_,
+ input waddr_4_,
+ input waddr_5_,
+ input a_0_,
+ input a_1_,
+ input a_2_,
+ input a_3_,
+ input a_4_,
+ input a_5_,
+ input a_6_,
+ input b_0_,
+ input b_1_,
+ input b_2_,
+ input b_3_,
+ input b_4_,
+ input b_5_,
+ input b_6_,
+ output q_0_,
+ output q_1_,
+ output q_2_,
+ output q_3_,
+ output q_4_,
+ output q_5_,
+ output q_6_,
+ output q_7_);
+
+ wire [5:0] raddr = { raddr_5_, raddr_4_, raddr_3_, raddr_2_, raddr_1_, raddr_0_ };
+ wire [5:0] waddr = { waddr_5_, waddr_4_, waddr_3_, waddr_2_, waddr_1_, waddr_0_ };
+ wire [6:0] a = { a_6_, a_5_, a_4_, a_3_, a_2_, a_1_, a_0_ };
+ wire [6:0] b = { b_6_, b_5_, b_4_, b_3_, b_2_, b_1_, b_0_ };
+ wire [7:0] q = { q_7_, q_6_, q_5_, q_4_, q_3_, q_2_, q_1_, q_0_ };
+
+ reg[7:0] ram[63:0];
+ reg[6:0] a_st0;
+ reg[6:0] a_st1;
+ reg[6:0] b_st0;
+ reg[6:0] b_st1;
+ reg[8:0] waddr_st0;
+ reg[8:0] waddr_st1;
+ reg wen_st0;
+ reg wen_st1;
+ reg[7:0] q_int;
+
+ wire[7:0] AplusB;
+
+ assign AplusB = a_st1 + b_st1;
+ assign q = q_int;
+
+ always@(posedge clk) begin
+ waddr_st0 <= waddr;
+ waddr_st1 <= waddr_st0;
+ a_st0 <= a;
+ a_st1 <= a_st0;
+ b_st0 <= b;
+ b_st1 <= b_st0;
+ wen_st0 <= wen;
+ wen_st1 <= wen_st0;
+ if(wen_st1) begin
+ ram[waddr_st1] <= AplusB;
+ end
+ if(ren) begin
+ q_int <= ram[raddr];
+ end
+ end
+
+endmodule
diff --git a/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf b/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf
new file mode 100644
index 000000000..b567b74e0
--- /dev/null
+++ b/openfpga_flow/tasks/heterogeneous_dpram/config/task.conf
@@ -0,0 +1,43 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = pipelined_8bit_adder
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/pipelined_8bit_adder/pipelined_8bit_adder.v
+bench0_chan_width = 100
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+min_route_chan_width=1.3
+vpr_fpga_verilog_include_icarus_simulator=
+vpr_fpga_verilog_formal_verification_top_netlist=
+vpr_fpga_verilog_include_timing=
+vpr_fpga_verilog_include_signal_init=
+vpr_fpga_verilog_print_autocheck_top_testbench=
+vpr_fpga_bitstream_generator=
+#vpr_fpga_verilog_print_user_defined_template=
+#vpr_fpga_verilog_print_report_timing_tcl=
+#vpr_fpga_verilog_print_sdc_pnr=
+#vpr_fpga_verilog_print_sdc_analysis=
+vpr_fpga_verilog_explicit_mapping=
+vpr_fpga_x2p_compact_routing_hierarchy=
+end_flow_with_test=
diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
index b8e8e8112..5b7abd0bb 100644
--- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
+++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_backannotate_utils.c
@@ -1480,6 +1480,10 @@ void update_one_grid_pack_net_num(int x, int y) {
assert ((NULL != type)
&& (EMPTY_TYPE != type)
&& (IO_TYPE != type));
+ /* Bypass grids whose offset is larger than 0 ! They have been processed! */
+ if (0 < grid[x][y].offset) {
+ return;
+ }
for (iblk = 0; iblk < grid[x][y].usage; iblk++) {
blk_id = grid[x][y].blocks[iblk];