From 56aaa6a1f4d413ce9ce48b29b240485ec6b91b4c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 19 May 2024 17:23:48 -0700 Subject: [PATCH] [core] sytax --- openfpga/src/fabric/build_routing_modules.cpp | 4 ++-- openfpga/src/fabric/build_tile_modules.cpp | 22 +++++++++++-------- .../fabric/build_top_module_connection.cpp | 4 ++-- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/openfpga/src/fabric/build_routing_modules.cpp b/openfpga/src/fabric/build_routing_modules.cpp index 952e97cf5..bc19f7a49 100644 --- a/openfpga/src/fabric/build_routing_modules.cpp +++ b/openfpga/src/fabric/build_routing_modules.cpp @@ -998,9 +998,9 @@ static void build_connection_block_module( std::vector cb_opin_sides = rr_gsb.get_cb_opin_sides(cb_type); for (size_t iside = 0; iside < cb_opin_sides.size(); ++iside) { enum e_side cb_opin_side = cb_opin_sides[iside]; - for (size_t inode = 0; inode < rr_gsb.get_num_cb_opin_nodes(cb_opin_side); + for (size_t inode = 0; inode < rr_gsb.get_num_cb_opin_nodes(cb_type, cb_opin_side); ++inode) { - RRNodeId opin_node = rr_gsb.get_cb_opin_node(cb_opin_side, inode); + RRNodeId opin_node = rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); std::string port_name = generate_cb_module_grid_port_name( cb_opin_side, grids, device_annotation, rr_graph, opin_node); BasicPort module_port(port_name, diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 7550a53e2..2ee93128d 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -478,7 +478,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( for (size_t inode = 0; inode < module_cb.get_num_cb_opin_nodes(cb_type, cb_opin_side); ++inode) { /* Collect source-related information */ - RRNodeId module_opin_node = module_cb.get_cb_opin_node(cb_type, cb_ipin_side, inode); + RRNodeId module_opin_node = module_cb.get_cb_opin_node(cb_type, cb_opin_side, inode); vtr::Point cb_src_port_coord( rr_graph.node_xlow(module_opin_node), rr_graph.node_ylow(module_opin_node)); @@ -495,7 +495,7 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( /* Note that we use the instance cb pin here!!! * because it has the correct coordinator for the grid!!! */ - RRNodeId instance_opin_node = rr_gsb.get_opin_node(cb_type, cb_opin_side, inode); + RRNodeId instance_opin_node = rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode); vtr::Point grid_coordinate( rr_graph.node_xlow(instance_opin_node), rr_graph.node_ylow(instance_opin_node)); @@ -575,17 +575,18 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( temp_sb_module_name = generate_switch_block_module_name_using_index(isb); } + /* FIXME: may find a way to determine the side. Currently using cb_opin_side is fine */ vtr::Point sink_sb_port_coord( rr_graph.node_xlow( - module_sb.get_opin_node(side_manager.get_side(), inode)), + module_sb.get_opin_node(cb_opin_side, inode)), rr_graph.node_ylow( - module_sb.get_opin_node(side_manager.get_side(), inode))); + module_sb.get_opin_node(cb_opin_side, inode))); std::string sink_sb_port_name = generate_sb_module_grid_port_name( - side_manager.get_side(), + cb_opin_side, get_rr_graph_single_node_side( - rr_graph, module_sb.get_opin_node(side_manager.get_side(), inode)), + rr_graph, module_sb.get_opin_node(cb_opin_side, inode)), grids, vpr_device_annotation, rr_graph, - module_sb.get_opin_node(side_manager.get_side(), inode)); + module_sb.get_opin_node(cb_opin_side, inode)); ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(sink_sb_module, @@ -593,15 +594,18 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( BasicPort sink_sb_port = module_manager.module_port(sink_sb_module, sink_sb_port_id); - src_grid_port.set_name(generate_tile_module_port_name( + sink_sb_port.set_name(generate_tile_module_port_name( temp_sb_module_name, sink_sb_port.get_name())); + ModulePortId src_tile_port_id = module_manager.find_module_port( + tile_module, sink_sb_port.get_name()); /* Create a net for each pin */ + VTR_ASSERT(src_cb_port.pins().size() == sink_sb_port.pins().size()); for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { ModuleNetId net = create_module_source_pin_net( module_manager, tile_module, tile_module, 0, src_tile_port_id, - src_grid_port.pins()[pin_id]); + sink_sb_port.pins()[pin_id]); /* Configure the net sink */ module_manager.add_module_net_sink( tile_module, net, src_cb_module, src_cb_instance, diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index d00496976..7e6728c69 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -576,7 +576,7 @@ static void add_top_module_nets_connect_grids_and_cb( rr_graph.node_xlow(module_opin_node), rr_graph.node_ylow(module_opin_node)); std::string src_cb_port_name = generate_cb_module_grid_port_name( - cb_ipin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); + cb_opin_side, grids, vpr_device_annotation, rr_graph, module_opin_node); ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(src_cb_module, @@ -619,7 +619,7 @@ static void add_top_module_nets_connect_grids_and_cb( std::string sink_grid_port_name = generate_grid_port_name( sink_grid_pin_width, sink_grid_pin_height, subtile_index, get_rr_graph_single_node_side( - rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, onode)), + rr_graph, rr_gsb.get_cb_opin_node(cb_type, cb_opin_side, inode)), sink_grid_pin_info); ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_grid_module, sink_grid_port_name);