From 56a3e6e4638417d989ecb5059fedf6a6db971820 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 30 Dec 2022 18:28:17 -0800 Subject: [PATCH] [test] reduce test size --- .../tasks/basic_tests/vpr_standalone/config/task.conf | 9 --------- 1 file changed, 9 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/vpr_standalone/config/task.conf b/openfpga_flow/tasks/basic_tests/vpr_standalone/config/task.conf index 9c1bf2f5e..1ab5cf4c4 100644 --- a/openfpga_flow/tasks/basic_tests/vpr_standalone/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/vpr_standalone/config/task.conf @@ -25,19 +25,10 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v [SYNTHESIS_PARAM] bench_read_verilog_options_common = -nolatches bench0_top = and2 -bench0_chan_width = 300 - -bench1_top = or2 -bench1_chan_width = 300 - -bench2_top = and2_latch -bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=