From 56284059de65ebc2c6063a6f7b3be00d52a1889a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Feb 2021 15:25:32 -0700 Subject: [PATCH] [Test] Add a test case for a super LUT --- .../config/bitstream_annotation.xml | 3 ++ .../frac_lut4_arith/config/task.conf | 38 +++++++++++++++++++ 2 files changed, 41 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml create mode 100644 openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml new file mode 100644 index 000000000..735d45c23 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml @@ -0,0 +1,3 @@ + + + diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf new file mode 100644 index 000000000..6244bd525 --- /dev/null +++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 1*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4_arith/config/bitstream_annotation.xml +openfpga_vpr_circuit_format=eblif + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.eblif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist=