[core] now bitgen uses config child types

openfpga/src/fabric/module_manager.cpp

@@ -241,7 +241,7 @@ ModuleManager::region_configurable_child_coordinates(
   for (const size_t& child_id :
        config_region_children_[parent_module][region]) {
     region_config_child_coordinates.push_back(
-      logical_configurable_child_coordinates_[parent_module][child_id]);
+      physical_configurable_child_coordinates_[parent_module][child_id]);
   }
 
   return region_config_child_coordinates;
@@ -657,6 +657,21 @@ bool ModuleManager::net_sink_exist(const ModuleId& module,
   return false;
 }
 
+bool ModuleManager::unified_configurable_children(const ModuleId& curr_module) const {
+  if (logical_configurable_children_[curr_module].size() != physical_configurable_children_[curr_module].size()) {
+    return false;
+  }
+  for (size_t ichild = 0; ichild < logical_configurable_children_[curr_module].size(); ++ichild) {
+    if (logical_configurable_children_[curr_module][ichild] != physical_configurable_children_[curr_module][ichild]) {
+      return false;
+    }
+    if (logical_configurable_child_instances_[curr_module][ichild] != physical_configurable_child_instances_[curr_module][ichild]) {
+      return false;
+    }
+  }
+  return true;
+}
+
 /******************************************************************************
  * Private Accessors
  ******************************************************************************/

openfpga/src/fabric/module_manager.h

@@ -323,6 +323,9 @@ class ModuleManager {
                       const ModuleId& sink_module, const size_t& instance_id,
                       const ModulePortId& sink_port, const size_t& sink_pin);
 
+  /** @brief Check if the configurable children under a given module are unified or not. If unified, it means that the logical configurable children are the same as the physical configurable children */
+  bool unified_configurable_children(const ModuleId& curr_module) const;
+
  private: /* Private accessors */
   size_t find_child_module_index_in_parent_module(
     const ModuleId& parent_module, const ModuleId& child_module) const;

openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp

@@ -74,12 +74,12 @@ static void rec_build_module_fabric_dependent_chain_bitstream(
     } else {
       for (size_t child_id = 0;
            child_id <
-           module_manager.logical_configurable_children(parent_module).size();
+           module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size();
            ++child_id) {
         ModuleId child_module =
-          module_manager.logical_configurable_children(parent_module)[child_id];
+          module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
         size_t child_instance =
-          module_manager.logical_configurable_child_instances(parent_module)[child_id];
+          module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
         /* Get the instance name and ensure it is not empty */
         std::string instance_name = module_manager.instance_name(
           parent_module, child_module, child_instance);
@@ -196,7 +196,7 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
        *   - no need to exclude decoders as they are not there
        */
       std::vector<ModuleId> configurable_children =
-        module_manager.logical_configurable_children(parent_module);
+        module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
 
       size_t num_configurable_children = configurable_children.size();
 
@@ -212,7 +212,7 @@ static void rec_build_module_fabric_dependent_memory_bank_bitstream(
            ++child_id) {
         ModuleId child_module = configurable_children[child_id];
         size_t child_instance =
-          module_manager.logical_configurable_child_instances(parent_module)[child_id];
+          module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
 
         /* Get the instance name and ensure it is not empty */
         std::string instance_name = module_manager.instance_name(
@@ -324,9 +324,9 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
     } else {
       VTR_ASSERT(top_module != parent_module);
       configurable_children =
-        module_manager.logical_configurable_children(parent_module);
+        module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
       configurable_child_instances =
-        module_manager.logical_configurable_child_instances(parent_module);
+        module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
     }
 
     size_t num_configurable_children = configurable_children.size();
@@ -361,9 +361,9 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
        * configurable children in all the regions
        */
       for (const ModuleId& child_module :
-           module_manager.logical_configurable_children(parent_module)) {
+           module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)) {
         /* Bypass any decoder module (which no configurable children */
-        if (module_manager.logical_configurable_children(child_module).empty()) {
+        if (module_manager.configurable_children(child_module, ModuleManager::e_config_child_type::PHYSICAL).empty()) {
           continue;
         }
         const ModulePortId& child_addr_port_id =
@@ -494,7 +494,7 @@ static void rec_build_module_fabric_dependent_frame_bitstream(
   } else {
     VTR_ASSERT(top_module != parent_modules.back());
     configurable_children =
-      module_manager.logical_configurable_children(parent_modules.back());
+      module_manager.configurable_children(parent_modules.back(), ModuleManager::e_config_child_type::PHYSICAL);
   }
 
   ModuleId decoder_module = configurable_children.back();

openfpga/src/fpga_bitstream/build_fabric_bitstream_memory_bank.cpp

@@ -123,7 +123,7 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
        *   - no need to exclude decoders as they are not there
        */
       std::vector<ModuleId> configurable_children =
-        module_manager.logical_configurable_children(parent_module);
+        module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL);
 
       size_t num_configurable_children = configurable_children.size();
 
@@ -139,7 +139,7 @@ static void rec_build_module_fabric_dependent_ql_memory_bank_regional_bitstream(
            ++child_id) {
         ModuleId child_module = configurable_children[child_id];
         size_t child_instance =
-          module_manager.logical_configurable_child_instances(parent_module)[child_id];
+          module_manager.configurable_child_instances(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[child_id];
 
         /* Get the instance name and ensure it is not empty */
         std::string instance_name = module_manager.instance_name(

openfpga/src/fpga_bitstream/build_grid_bitstream.cpp

@@ -644,16 +644,18 @@ static void rec_build_physical_block_bitstream(
    * manager */
   std::string pb_block_name = generate_physical_block_instance_name(
     physical_pb_type, pb_graph_node_index);
-  ConfigBlockId pb_configurable_block =
+  /* If there are no physical memory blocks under the current module, use the previous module, which is the physical memory block */
-    bitstream_manager.add_block(pb_block_name);
+  ConfigBlockId pb_configurable_block = parent_configurable_block;
-  bitstream_manager.add_child_block(parent_configurable_block,
+  if (0 < module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::PHYSICAL)) {
-                                    pb_configurable_block);
+    pb_configurable_block = bitstream_manager.add_block(pb_block_name);
-
+    bitstream_manager.add_child_block(parent_configurable_block,
-  /* Reserve child blocks for new created block */
+                                      pb_configurable_block);
-  bitstream_manager.reserve_child_blocks(
+    /* Reserve child blocks for new created block */
-    parent_configurable_block,
+    bitstream_manager.reserve_child_blocks(
-    count_module_manager_module_configurable_children(module_manager,
+      parent_configurable_block,
-                                                      pb_module, ModuleManager::e_config_child_type::PHYSICAL));
+      count_module_manager_module_configurable_children(module_manager,
+                                                        pb_module, ModuleManager::e_config_child_type::PHYSICAL));
+  }
 
   /* Recursively finish all the child pb_types*/
   if (false == is_primitive_pb_type(physical_pb_type)) {
@@ -772,6 +774,15 @@ static void build_physical_block_bitstream(
     grid_configurable_block, count_module_manager_module_configurable_children(
                                module_manager, grid_module, ModuleManager::e_config_child_type::PHYSICAL));
 
+  /* Create a dedicated block for the non-unified configurable child */
+  if (!module_manager.unified_configurable_children(grid_module)) {
+    VTR_ASSERT(1 == module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL).size());
+    std::string phy_mem_instance_name = module_manager.instance_name(grid_module, module_manager.configurable_children(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(grid_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
+    ConfigBlockId grid_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
+    bitstream_manager.add_child_block(grid_configurable_block, grid_grouped_config_block);
+    grid_configurable_block = grid_grouped_config_block;
+  }
+
   /* Iterate over the capacity of the grid
    * Now each physical tile may have a number of logical blocks
    * OpenFPGA only considers the physical implementation of the tiles.

openfpga/src/fpga_bitstream/build_routing_bitstream.cpp

@@ -487,7 +487,7 @@ static void build_connection_block_bitstreams(
 
       /* Bypass empty blocks which have none configurable children */
       if (0 == count_module_manager_module_configurable_children(module_manager,
-                                                                 cb_module)) {
+                                                                 cb_module, ModuleManager::e_config_child_type::LOGICAL)) {
         continue;
       }
 
@@ -528,7 +528,16 @@ static void build_connection_block_bitstreams(
       bitstream_manager.reserve_child_blocks(
         cb_configurable_block,
         count_module_manager_module_configurable_children(module_manager,
-                                                          cb_module));
+                                                          cb_module, ModuleManager::e_config_child_type::PHYSICAL));
+
+      /* Create a dedicated block for the non-unified configurable child */
+      if (!module_manager.unified_configurable_children(cb_module)) {
+        VTR_ASSERT(1 == module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
+        std::string phy_mem_instance_name = module_manager.instance_name(cb_module, module_manager.configurable_children(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(cb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
+        ConfigBlockId cb_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
+        bitstream_manager.add_child_block(cb_configurable_block, cb_grouped_config_block);
+        cb_configurable_block = cb_grouped_config_block;
+      }
 
       build_connection_block_bitstream(
         bitstream_manager, cb_configurable_block, module_manager, circuit_lib,
@@ -594,7 +603,7 @@ void build_routing_bitstream(
 
       /* Bypass empty blocks which have none configurable children */
       if (0 == count_module_manager_module_configurable_children(module_manager,
-                                                                 sb_module)) {
+                                                                 sb_module, ModuleManager::e_config_child_type::LOGICAL)) {
         continue;
       }
 
@@ -630,7 +639,16 @@ void build_routing_bitstream(
       bitstream_manager.reserve_child_blocks(
         sb_configurable_block,
         count_module_manager_module_configurable_children(module_manager,
-                                                          sb_module));
+                                                          sb_module, ModuleManager::e_config_child_type::PHYSICAL));
+
+      /* Create a dedicated block for the non-unified configurable child */
+      if (!module_manager.unified_configurable_children(sb_module)) {
+        VTR_ASSERT(1 == module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL).size());
+        std::string phy_mem_instance_name = module_manager.instance_name(sb_module, module_manager.configurable_children(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0], module_manager.configurable_child_instances(sb_module, ModuleManager::e_config_child_type::PHYSICAL)[0]);
+        ConfigBlockId sb_grouped_config_block = bitstream_manager.add_child_block(phy_mem_instance_name);
+        bitstream_manager.add_child_block(sb_configurable_block, sb_grouped_config_block);
+        sb_configurable_block = sb_grouped_config_block;
+      }
 
       build_switch_block_bitstream(bitstream_manager, sb_configurable_block,
                                    module_manager, circuit_lib, mux_lib,