From 56113e1aab428e791f58dd234a0ca40c994489bd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 14 Jan 2020 14:10:00 -0700 Subject: [PATCH] adding XML parsing for design tech of circuit model --- .../libarchopenfpga/arch/sample_arch.xml | 16 ++-- .../src/read_xml_circuit_library.cpp | 84 +++++++++++++++---- vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- 3 files changed, 76 insertions(+), 26 deletions(-) diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml index d9c845f45..3dec02660 100644 --- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml +++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml @@ -43,7 +43,7 @@ - + @@ -54,7 +54,7 @@ 10e-12 - + @@ -65,7 +65,7 @@ 10e-12 - + @@ -76,7 +76,7 @@ 10e-12 - + @@ -91,7 +91,7 @@ 10e-12 5e-12 5e-12 - + @@ -105,7 +105,7 @@ 10e-12 10e-12 - + @@ -113,7 +113,7 @@ - + @@ -141,7 +141,7 @@ - + diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index f55084681..4bb454265 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -72,23 +72,69 @@ e_circuit_model_type string_to_circuit_model_type(const std::string& type_string return NUM_CIRCUIT_MODEL_TYPES; } +/******************************************************************** + * Convert string to the enumerate of model type + *******************************************************************/ +static +e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_string) { + if (std::string("cmos") == type_string) { + return CIRCUIT_MODEL_DESIGN_CMOS; + } + + if (std::string("rram") == type_string) { + return CIRCUIT_MODEL_DESIGN_RRAM; + } + + return NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES; +} + +/******************************************************************** + * Parse XML codes of design technology of a circuit model to circuit library + *******************************************************************/ +static +void read_xml_model_design_technology(pugi::xml_node& xml_model, + const pugiutil::loc_data& loc_data, + CircuitLibrary& circuit_lib, const CircuitModelId& model) { + + auto xml_design_tech = get_single_child(xml_model, "design_technology", loc_data); + + /* Identify if the circuit model power-gated */ + circuit_lib.set_model_is_power_gated(model, get_attribute(xml_design_tech, "power_gated", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + + /* Identify the type of design technology */ + const char* type_attr = get_attribute(xml_design_tech, "type", loc_data).value(); + /* Translate the type of design technology to enumerate */ + e_circuit_model_design_tech design_tech_type = string_to_design_tech_type(std::string(type_attr)); + + if (NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES == design_tech_type) { + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_design_tech), + "Invalid 'type' attribute '%s'\n", + type_attr); + } + + circuit_lib.set_model_design_tech_type(model, design_tech_type); + + /* Parse exclusive attributes for inverters and buffers */ + +} + /******************************************************************** * Parse XML codes of a circuit model to circuit library *******************************************************************/ static -void read_xml_circuit_model(pugi::xml_node& model_xml, +void read_xml_circuit_model(pugi::xml_node& xml_model, const pugiutil::loc_data& loc_data, CircuitLibrary& circuit_lib) { /* Find the type of the circuit model * so that we can add a new circuit model to circuit library */ - const char* type_attr = get_attribute(model_xml, "type", loc_data).value(); + const char* type_attr = get_attribute(xml_model, "type", loc_data).value(); /* Translate the type of circuit model to enumerate */ e_circuit_model_type model_type = string_to_circuit_model_type(std::string(type_attr)); if (NUM_CIRCUIT_MODEL_TYPES == model_type) { - archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_xml), + archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_model), "Invalid 'type' attribute '%s'\n", type_attr); } @@ -96,27 +142,31 @@ void read_xml_circuit_model(pugi::xml_node& model_xml, CircuitModelId model = circuit_lib.add_model(model_type); /* Find the name of the circuit model */ - const char* name_attr = get_attribute(model_xml, "name", loc_data).value(); + const char* name_attr = get_attribute(xml_model, "name", loc_data).value(); circuit_lib.set_model_name(model, std::string(name_attr)); /* TODO: This attribute is going to be DEPRECATED * Find the prefix of the circuit model */ - const char* prefix_attr = get_attribute(model_xml, "prefix", loc_data).value(); + const char* prefix_attr = get_attribute(xml_model, "prefix", loc_data).value(); circuit_lib.set_model_prefix(model, std::string(prefix_attr)); /* Find a SPICE netlist which is an optional attribute*/ - const char* spice_netlist_attr = get_attribute(model_xml, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr); - if (spice_netlist_attr) { - circuit_lib.set_model_circuit_netlist(model, std::string(spice_netlist_attr)); - } + circuit_lib.set_model_circuit_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string("")); /* Find a Verilog netlist which is an optional attribute*/ - const char* verilog_netlist_attr = get_attribute(model_xml, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr); - if (verilog_netlist_attr) { - circuit_lib.set_model_verilog_netlist(model, std::string(verilog_netlist_attr)); - } + circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string("")); + /* Find if the circuit model is default in its type */ + circuit_lib.set_model_is_default(model, get_attribute(xml_model, "is_default", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + + /* Find if the circuit model is should be dumped in structural verilog */ + circuit_lib.set_model_dump_structural_verilog(model, get_attribute(xml_model, "dump_structural_verilog", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + + /* Parse attributes under the */ + /* Design technology -related attributes */ + read_xml_model_design_technology(xml_model, loc_data, circuit_lib, model); + } /******************************************************************** @@ -129,12 +179,12 @@ CircuitLibrary read_xml_circuit_library(pugi::xml_node& Node, /* Iterate over the children under this node, * each child should be named after circuit_model */ - for (pugi::xml_node model_xml : Node.children()) { + for (pugi::xml_node xml_model : Node.children()) { /* Error out if the XML child has an invalid name! */ - if (model_xml.name() != std::string("circuit_model")) { - bad_tag(model_xml, loc_data, Node, {"circuit_model"}); + if (xml_model.name() != std::string("circuit_model")) { + bad_tag(xml_model, loc_data, Node, {"circuit_model"}); } - read_xml_circuit_model(model_xml, loc_data, circuit_lib); + read_xml_circuit_model(xml_model, loc_data, circuit_lib); } return circuit_lib; diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index 01051486e..8df9df422 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/* ../../libpcre/SRC/*.[ch] ../../../libs/libvtrutil/src/* +ctags -R shell_main.c main.c ./* ../../libarchfpgavpr7/SRC/* ../../libpcre/SRC/*.[ch] ../../../libs/libvtrutil/src/*