diff --git a/libopenfpga/libarchopenfpga/arch/sample_arch.xml b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
index d9c845f45..3dec02660 100644
--- a/libopenfpga/libarchopenfpga/arch/sample_arch.xml
+++ b/libopenfpga/libarchopenfpga/arch/sample_arch.xml
@@ -43,7 +43,7 @@
     <io_pmos model_name="pch_25" chan_length="270e-9" min_width="320e-9"/>
   </transistors>
   <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="1">
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1" tapered="off"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -54,7 +54,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="0">
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="2" f_per_stage="4"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -65,7 +65,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="0">
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" tapered="on" tap_drive_level="3" f_per_stage="4"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
@@ -76,7 +76,7 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="1">
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
       <input_buffer exist="off"/>
       <output_buffer exist="off"/>
@@ -91,7 +91,7 @@
         10e-12 5e-12 5e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="1">
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
       <design_technology type="cmos" topology="OR"/>
       <input_buffer exist="off"/>
       <output_buffer exist="off"/>
@@ -105,7 +105,7 @@
         10e-12 10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="1">
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
       <design_technology type="cmos"/>
       <input_buffer exist="off"/>
       <output_buffer exist="off"/>
@@ -113,7 +113,7 @@
       <port type="output" prefix="out" size="1"/>
       <wire_param model_type="pie" res_val="101" cap_val="22.5e-15" level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
     </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="1">
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
       <design_technology type="cmos"/>
       <input_buffer exist="off"/>
       <output_buffer exist="off"/>
@@ -141,7 +141,7 @@
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="1" dump_structural_verilog="true">
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
       <design_technology type="cmos" structure="one-level" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="on" circuit_model_name="INVTX1"/>
       <output_buffer exist="on" circuit_model_name="tap_buf4"/>
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index f55084681..4bb454265 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -72,23 +72,69 @@ e_circuit_model_type string_to_circuit_model_type(const std::string& type_string
   return NUM_CIRCUIT_MODEL_TYPES;
 }
 
+/********************************************************************
+ * Convert string to the enumerate of model type
+ *******************************************************************/
+static 
+e_circuit_model_design_tech string_to_design_tech_type(const std::string& type_string) {
+  if (std::string("cmos") == type_string) {
+    return CIRCUIT_MODEL_DESIGN_CMOS;
+  }
+
+  if (std::string("rram") == type_string) {
+    return CIRCUIT_MODEL_DESIGN_RRAM;
+  }
+
+  return NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES;
+}
+
+/********************************************************************
+ * Parse XML codes of design technology of a circuit model to circuit library
+ *******************************************************************/
+static 
+void read_xml_model_design_technology(pugi::xml_node& xml_model,
+                                      const pugiutil::loc_data& loc_data,
+                                      CircuitLibrary& circuit_lib, const CircuitModelId& model) {
+
+  auto xml_design_tech = get_single_child(xml_model, "design_technology", loc_data); 
+
+  /* Identify if the circuit model power-gated */
+  circuit_lib.set_model_is_power_gated(model, get_attribute(xml_design_tech, "power_gated", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
+
+  /* Identify the type of design technology */
+  const char* type_attr = get_attribute(xml_design_tech, "type", loc_data).value();
+  /* Translate the type of design technology to enumerate */
+  e_circuit_model_design_tech design_tech_type = string_to_design_tech_type(std::string(type_attr));
+
+  if (NUM_CIRCUIT_MODEL_DESIGN_TECH_TYPES == design_tech_type) {
+    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_design_tech),
+                   "Invalid 'type' attribute '%s'\n",
+                   type_attr);
+  }
+
+  circuit_lib.set_model_design_tech_type(model, design_tech_type);
+   
+  /* Parse exclusive attributes for inverters and buffers */
+  
+}
+
 /********************************************************************
  * Parse XML codes of a circuit model to circuit library
  *******************************************************************/
 static 
-void read_xml_circuit_model(pugi::xml_node& model_xml,
+void read_xml_circuit_model(pugi::xml_node& xml_model,
                             const pugiutil::loc_data& loc_data,
                             CircuitLibrary& circuit_lib) {
   /* Find the type of the circuit model
    * so that we can add a new circuit model to circuit library 
    */
-  const char* type_attr = get_attribute(model_xml, "type", loc_data).value();
+  const char* type_attr = get_attribute(xml_model, "type", loc_data).value();
 
   /* Translate the type of circuit model to enumerate */
   e_circuit_model_type model_type = string_to_circuit_model_type(std::string(type_attr));
 
   if (NUM_CIRCUIT_MODEL_TYPES == model_type) {
-    archfpga_throw(loc_data.filename_c_str(), loc_data.line(model_xml),
+    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_model),
                    "Invalid 'type' attribute '%s'\n",
                    type_attr);
   }
@@ -96,27 +142,31 @@ void read_xml_circuit_model(pugi::xml_node& model_xml,
   CircuitModelId model = circuit_lib.add_model(model_type);
 
   /* Find the name of the circuit model */
-  const char* name_attr = get_attribute(model_xml, "name", loc_data).value();
+  const char* name_attr = get_attribute(xml_model, "name", loc_data).value();
   circuit_lib.set_model_name(model, std::string(name_attr));
 
   /* TODO: This attribute is going to be DEPRECATED 
    * Find the prefix of the circuit model
    */
-  const char* prefix_attr = get_attribute(model_xml, "prefix", loc_data).value();
+  const char* prefix_attr = get_attribute(xml_model, "prefix", loc_data).value();
   circuit_lib.set_model_prefix(model, std::string(prefix_attr));
 
   /* Find a SPICE netlist which is an optional attribute*/
-  const char* spice_netlist_attr = get_attribute(model_xml, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr);
-  if (spice_netlist_attr) {
-    circuit_lib.set_model_circuit_netlist(model, std::string(spice_netlist_attr));
-  }
+  circuit_lib.set_model_circuit_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
 
   /* Find a Verilog netlist which is an optional attribute*/
-  const char* verilog_netlist_attr = get_attribute(model_xml, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr);
-  if (verilog_netlist_attr) {
-    circuit_lib.set_model_verilog_netlist(model, std::string(verilog_netlist_attr));
-  }
+  circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
 
+  /* Find if the circuit model is default in its type */
+  circuit_lib.set_model_is_default(model, get_attribute(xml_model, "is_default", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
+  
+  /* Find if the circuit model is should be dumped in structural verilog */
+  circuit_lib.set_model_dump_structural_verilog(model, get_attribute(xml_model, "dump_structural_verilog", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
+
+  /* Parse attributes under the <circuit_model> */
+  /* Design technology -related attributes */
+  read_xml_model_design_technology(xml_model, loc_data, circuit_lib, model);
+  
 }
 
 /********************************************************************
@@ -129,12 +179,12 @@ CircuitLibrary read_xml_circuit_library(pugi::xml_node& Node,
   /* Iterate over the children under this node,
    * each child should be named after circuit_model
    */
-  for (pugi::xml_node model_xml : Node.children()) {
+  for (pugi::xml_node xml_model : Node.children()) {
     /* Error out if the XML child has an invalid name! */
-    if (model_xml.name() != std::string("circuit_model")) {
-      bad_tag(model_xml, loc_data, Node, {"circuit_model"});
+    if (xml_model.name() != std::string("circuit_model")) {
+      bad_tag(xml_model, loc_data, Node, {"circuit_model"});
     }
-    read_xml_circuit_model(model_xml, loc_data, circuit_lib);
+    read_xml_circuit_model(xml_model, loc_data, circuit_lib);
   } 
 
   return circuit_lib;
diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh
index 01051486e..8df9df422 100755
--- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh
+++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh
@@ -1,2 +1,2 @@
 rm tags
-ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/* ../../libpcre/SRC/*.[ch] ../../../libs/libvtrutil/src/*
+ctags -R shell_main.c main.c ./* ../../libarchfpgavpr7/SRC/* ../../libpcre/SRC/*.[ch] ../../../libs/libvtrutil/src/*