From 55fbd72293d8a52b0d33aa428145d00e7bddd4c4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 30 Oct 2019 15:50:42 -0600 Subject: [PATCH] many bugs have been fixed --- .../tasks/blif_vpr_flow/config/task.conf | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp | 6 ++- .../verilog/verilog_preconfig_top_module.cpp | 41 ++++++++++++------- .../verilog/verilog_preconfig_top_module.h | 1 - .../fpga_x2p/verilog/verilog_writer_utils.cpp | 18 ++++++++ .../fpga_x2p/verilog/verilog_writer_utils.h | 4 ++ 7 files changed, 55 insertions(+), 18 deletions(-) diff --git a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf index 7cadfce2c..16fab45de 100644 --- a/openfpga_flow/tasks/blif_vpr_flow/config/task.conf +++ b/openfpga_flow/tasks/blif_vpr_flow/config/task.conf @@ -60,6 +60,7 @@ vpr_fpga_verilog_print_user_defined_template= vpr_fpga_verilog_print_report_timing_tcl= vpr_fpga_verilog_print_sdc_pnr= vpr_fpga_verilog_print_sdc_analysis= +vpr_fpga_verilog_explicit_mapping= #vpr_fpga_x2p_compact_routing_hierarchy= end_flow_with_test= diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 844abd25d..bb5af9ac5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -410,7 +410,7 @@ void vpr_fpga_verilog(ModuleManager& module_manager, dump_verilog_formal_verification_top_netlist(sram_verilog_orgz_info, chomped_circuit_name, std::string(formal_verification_top_netlist_file_path + std::string(".bak")).c_str(), src_dir_path); /* TODO: new function: to be tested */ - print_verilog_preconfig_top_module(module_manager, bitstream_manager, fabric_bitstream, + print_verilog_preconfig_top_module(module_manager, bitstream_manager, Arch.spice->circuit_lib, global_ports, L_logical_blocks, device_size, L_grids, L_blocks, std::string(chomped_circuit_name), formal_verification_top_netlist_file_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp index 3f5656b4a..401484e30 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_grid.cpp @@ -141,12 +141,14 @@ void print_verilog_physical_blocks_rec(std::fstream& fp, } } - /* For leaf node, a primitive Verilog module will be generated */ + /* For leaf node, a primitive Verilog module will be generated. + * Note that the primitive may be mapped to a standard cell, we force to use that + */ if (TRUE == is_primitive_pb_type(physical_pb_type)) { print_verilog_primitive_block(fp, module_manager, physical_pb_graph_node, io_side, - use_explicit_mapping); + true); /* Finish for primitive node, return */ return; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp index d3bf11bb2..731a3630e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.cpp @@ -271,14 +271,17 @@ static void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, - const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream) { + const BitstreamManager& bitstream_manager) { print_verilog_comment(fp, std::string("----- Begin load bitstream to configuration memories -----")); + fp << "initial begin" << std::endl; - for (const ConfigBitId& config_bit_id : fabric_bitstream) { - ConfigBlockId bit_parent_block = bitstream_manager.bit_parent_block(config_bit_id); + for (const ConfigBlockId& config_block_id : bitstream_manager.blocks()) { + /* We only cares blocks with configuration bits */ + if (0 == bitstream_manager.block_bits(config_block_id).size()) { + continue; + } /* Build the hierarchical path of the configuration bit in modules */ - std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, bit_parent_block); + std::vector block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block_id); /* Drop the first block, which is the top module, it should be replaced by the instance name here */ /* Ensure that this is the module we want to drop! */ VTR_ASSERT(0 == module_manager.module_name(top_module).compare(bitstream_manager.block_name(block_hierarchy[0]))); @@ -290,18 +293,29 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, bit_hierarchy_path += bitstream_manager.block_name(temp_block); } bit_hierarchy_path += std::string("."); - bit_hierarchy_path += generate_configuration_chain_data_out_name(); /* Find the bit index in the parent block */ - BasicPort config_port(bit_hierarchy_path, - bitstream_manager.bit_index_in_parent_block(config_bit_id), - bitstream_manager.bit_index_in_parent_block(config_bit_id)); + BasicPort config_data_port(bit_hierarchy_path + generate_configuration_chain_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); - /* Wire it to the configuration bit */ - std::vector default_values(config_port.get_width(), bitstream_manager.bit_value(config_bit_id)); - print_verilog_wire_constant_values(fp, config_port, default_values); + BasicPort config_datab_port(bit_hierarchy_path + generate_configuration_chain_inverted_data_out_name(), + bitstream_manager.block_bits(config_block_id).size()); + + /* Wire it to the configuration bit: access both data out and data outb ports */ + std::vector config_data_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_data_values.push_back(bitstream_manager.bit_value(config_bit)); + } + print_verilog_deposit_wire_constant_values(fp, config_data_port, config_data_values); + + std::vector config_datab_values; + for (const ConfigBitId config_bit : bitstream_manager.block_bits(config_block_id)) { + config_datab_values.push_back(!bitstream_manager.bit_value(config_bit)); + } + print_verilog_deposit_wire_constant_values(fp, config_datab_port, config_datab_values); } + fp << "end" << std::endl; print_verilog_comment(fp, std::string("----- End load bitstream to configuration memories -----")); } @@ -340,7 +354,6 @@ void print_verilog_preconfig_top_module_load_bitstream(std::fstream& fp, *******************************************************************/ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const std::vector& L_logical_blocks, @@ -401,7 +414,7 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, /* Assign FPGA internal SRAM/Memory ports to bitstream values */ print_verilog_preconfig_top_module_load_bitstream(fp, module_manager, top_module, - bitstream_manager, fabric_bitstream); + bitstream_manager); /* Testbench ends*/ print_verilog_module_end(fp, std::string(circuit_name) + std::string(formal_verification_top_module_postfix)); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h index 441de0836..aae0a5c67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_preconfig_top_module.h @@ -10,7 +10,6 @@ void print_verilog_preconfig_top_module(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, - const std::vector& fabric_bitstream, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const std::vector& L_logical_blocks, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp index b6c8bdd0a..e119fa2ad 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.cpp @@ -665,6 +665,24 @@ void print_verilog_wire_constant_values(std::fstream& fp, fp << ";" << std::endl; } +/******************************************************************** + * Deposit constant values to a Verilog port + *******************************************************************/ +void print_verilog_deposit_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values) { + /* Make sure we have a valid file handler*/ + check_file_handler(fp); + + fp << "\t"; + fp << "$deposit("; + fp << generate_verilog_port(VERILOG_PORT_CONKT, output_port); + fp << ", "; + fp << generate_verilog_constant_values(const_values); + fp << ");" << std::endl; +} + + /******************************************************************** * Generate a wire connection for two Verilog ports * using "assign" syntax diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h index 6040cb07f..62724f36b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_writer_utils.h @@ -88,6 +88,10 @@ void print_verilog_wire_constant_values(std::fstream& fp, const BasicPort& output_port, const std::vector& const_values); +void print_verilog_deposit_wire_constant_values(std::fstream& fp, + const BasicPort& output_port, + const std::vector& const_values); + void print_verilog_wire_connection(std::fstream& fp, const BasicPort& output_port, const BasicPort& input_port,