From 2d92a1f1af7b854436caf89d88b475a4b7152028 Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Fri, 2 Oct 2020 10:18:10 -0400 Subject: [PATCH 1/5] Edits to enable basic run_fpga_flow.py --- openfpga_flow/misc/fpgaflow_default_tool_path.conf | 6 +++--- openfpga_flow/scripts/run_fpga_flow.py | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 5b89052e3..ec5d4db6b 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -7,11 +7,11 @@ odin2_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/not_used_atm/odin2.exe abc_path = ${PATH:OPENFPGA_PATH}/yosys/yosys-abc abc_mccl_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc abc_with_bb_support_path = ${PATH:OPENFPGA_PATH}/abc_with_bb_support/abc -vpr_path = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/vpr +vpr_path = ${PATH:OPENFPGA_PATH}/vpr/vpr ace_path = ${PATH:OPENFPGA_PATH}/ace2/ace pro_blif_path = ${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/pro_blif.pl iverilog_path = iverilog -include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists +include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr/VerilogNetlists [FLOW_SCRIPT_CONFIG] valid_flows = standard,vpr_blif,vtr,vtr_standard,yosys_vpr @@ -68,4 +68,4 @@ vvp_output=vvp_sim_output.txt [CMD_ARGUMENT_DEPENDANCY] vpr_fpga_verilog=vpr_fpga_verilog_dir|abc -vpr_fpga_verilog_dir=vpr_fpga_verilog \ No newline at end of file +vpr_fpga_verilog_dir=vpr_fpga_verilog diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a331d506d..46b242a75 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -672,7 +672,7 @@ def run_vpr(): min_channel_width) extract_vpr_stats(args.top_module+"_fr_chan_width_vpr.txt") else: - extract_vpr_stats(args.top_module+"_min_chan_width.txt") + extract_vpr_stats(args.top_module+"_min_chan_width_vpr.txt") if args.power: extract_vpr_stats(logfile=args.top_module+".power", r_filename="vpr_power_stat", @@ -716,11 +716,11 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): "--net_file", args.top_module+"_vpr.net", "--place_file", args.top_module+"_vpr.place", "--route_file", args.top_module+"_vpr.route", - "--full_stats", + "--full_stats", "on", "--activity_file", args.top_module+"_ace_out.act", ] if not args.disp: - command += ["--nodisp"] + command += ["--disp", "off"] if route_only: command += ["--route"] # Power options From d68427e47bedffa273a2d80eb1569697318e8222 Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Mon, 5 Oct 2020 21:35:22 -0400 Subject: [PATCH 2/5] Fixed blif formatting bug --- openfpga_flow/scripts/run_fpga_flow.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a331d506d..355187e1a 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -622,7 +622,7 @@ def run_vpr(): args.top_module, args.top_module) cmd += r"| sed 's/$/./' | fold -s -w80 " - cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$/ /'" + cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$//'" cmd += " > %s.blif" % args.top_module os.system(cmd) if not args.fix_route_chan_width: From 00295a003fb824eac349e13adbde9bdff14527dc Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Mon, 5 Oct 2020 16:27:08 -0400 Subject: [PATCH 3/5] Docs: Updated note to enable VPR's GUI --- docs/source/tutorials/compile.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/source/tutorials/compile.rst b/docs/source/tutorials/compile.rst index cab9ffdd2..fc9a25b13 100644 --- a/docs/source/tutorials/compile.rst +++ b/docs/source/tutorials/compile.rst @@ -23,6 +23,8 @@ In general, please follow the steps to compile .. note:: recommand to use ``make -j`` to accelerate the compilation +.. note:: VPR's GUI requires gtk-3, and can be enabled with ``cmake .. -DVPR_USE_EZGL=on`` + **Quick Compilation Verification** To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository From 33bbe0ec489805098101b10f713cc4d9e140f25f Mon Sep 17 00:00:00 2001 From: Andrew Lukefahr Date: Tue, 6 Oct 2020 15:09:22 -0400 Subject: [PATCH 4/5] FLOW: fixed display flag --- openfpga_flow/scripts/run_fpga_flow.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 46b242a75..223b20190 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -596,7 +596,7 @@ def run_pro_blif_3arg(): def collect_files_for_vpr(): # Sanitize provided Benchmark option if len(args.benchmark_files) > 1: - logger.error("Expecting Single Benchmark BLif file.") + logger.error("Expecting Single Benchmark Blif file.") if not os.path.isfile(args.benchmark_files[0] or ""): clean_up_and_exit("Provided Blif file not found") shutil.copy(args.benchmark_files[0], args.top_module+".blif") @@ -721,6 +721,9 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): ] if not args.disp: command += ["--disp", "off"] + else: + command += ["--disp", "on"] + if route_only: command += ["--route"] # Power options From 468c3ff3538d7b1d01ff1deb8c9f86ad559d0f23 Mon Sep 17 00:00:00 2001 From: Olof Kindgren Date: Fri, 6 Nov 2020 09:53:11 +0100 Subject: [PATCH 5/5] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 56b4598d6..5a8a9e960 100644 --- a/README.md +++ b/README.md @@ -4,7 +4,7 @@ ## Introduction -The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. +The award-winning OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers. A quick overview of OpenFPGA tools can be found [**here**](https://openfpga.readthedocs.io/en/master/tutorials/tools.html). We also recommend potential users to checkout the summary of [**technical capabilities**](https://openfpga.readthedocs.io/en/master/overview/tech_highlights.html) before compiling.