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update regression test with no-explicit port mapping cases

This commit is contained in:
tangxifan 2019-10-30 19:37:06 -06:00
parent 7460dc8cab
commit 5531422186
1 changed files with 1 additions and 1 deletions
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2
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
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@ -60,7 +60,7 @@ vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
vpr_fpga_verilog_explicit_mapping=
#vpr_fpga_verilog_explicit_mapping=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=