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[FPGA-Verilog] Bug fix in code generator

This commit is contained in:
tangxifan 2021-10-02 17:31:37 -07:00
parent 32fc0a1692
commit 54ec74d8d2
1 changed files with 2 additions and 3 deletions
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5
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
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@ -350,7 +350,6 @@ void print_verilog_full_testbench_ql_memory_bank_shift_register_clock_generator(
fp << "\t\t"; fp << "\t\t";
fp << "#0.05 "; fp << "#0.05 ";
print_verilog_register_connection(fp, sr_clock_port, sr_clock_port, true); print_verilog_register_connection(fp, sr_clock_port, sr_clock_port, true);
fp << ";" << std::endl;
fp << "\t"; fp << "\t";
fp << "end"; fp << "end";
@ -552,7 +551,7 @@ void print_verilog_full_testbench_ql_memory_bank_shift_register_bitstream(std::f
fp << "\t\t"; fp << "\t\t";
fp << generate_verilog_port_constant_values(start_bl_sr_port, std::vector<size_t>(start_bl_sr_port.get_width(), 0), true); fp << generate_verilog_port_constant_values(start_bl_sr_port, std::vector<size_t>(start_bl_sr_port.get_width(), 0), true);
fp << std::endl; fp << ";" << std::endl;
fp << "\t\t"; fp << "\t\t";
fp << TOP_TB_BL_SHIFT_REGISTER_COUNT_PORT_NAME << " = 0;"; fp << TOP_TB_BL_SHIFT_REGISTER_COUNT_PORT_NAME << " = 0;";
@ -583,7 +582,7 @@ void print_verilog_full_testbench_ql_memory_bank_shift_register_bitstream(std::f
fp << "\t\t"; fp << "\t\t";
fp << generate_verilog_port_constant_values(start_wl_sr_port, std::vector<size_t>(start_wl_sr_port.get_width(), 0), true); fp << generate_verilog_port_constant_values(start_wl_sr_port, std::vector<size_t>(start_wl_sr_port.get_width(), 0), true);
fp << std::endl; fp << ";" << std::endl;
fp << "\t\t"; fp << "\t\t";
fp << TOP_TB_WL_SHIFT_REGISTER_COUNT_PORT_NAME << " = 0;"; fp << TOP_TB_WL_SHIFT_REGISTER_COUNT_PORT_NAME << " = 0;";