diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v
deleted file mode 100644
index 2f2477f24..000000000
--- a/openfpga_flow/VerilogNetlists/ff.v
+++ /dev/null
@@ -1,146 +0,0 @@
-//-----------------------------------------------------
-// Design Name : static_dff
-// File Name   : ff.v
-// Function    : D flip-flop with asyn reset and set
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-//------ Include defines: preproc flags -----
-// `include "./SRC/fpga_defines.v"
-module static_dff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-
-endmodule //End Of Module static_dff
-
-module scan_chain_ff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-input TESTEN, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-input DI, // Scan Chain Data Input
-output Q // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else if (TESTEN) begin
-  q_reg <= DI;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-
-endmodule //End Of Module static_dff
-
-
-//-----------------------------------------------------
-// Design Name : scan_chain_dff
-// File Name   : ff.v
-// Function    : D flip-flop with asyn reset and set
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module sc_dff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q, // Q output
-output Qb // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~Q;
-
-endmodule //End Of Module static_dff
-
-//-----------------------------------------------------
-// Design Name : scan_chain_dff compact
-// File Name   : ff.v
-// Function    : Scan-chain D flip-flop without reset and set	//Modified to fit Edouards architecture
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module sc_dff_compact (
-/* Global ports go first */
-input reset, // Reset input
-//input set,     // set input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q, // Q output
-output Qb // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset /*or posedge set*/)
-if (reset) begin
-  q_reg <= 1'b0;
-//end else if (set) begin
-//  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-/*
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~Q;
-*/
-
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~q_reg;
-`else
-assign Q = 1'bZ;
-assign Qb = !Q;
-`endif
-
-endmodule //End Of Module static_dff
diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v
deleted file mode 100644
index 11b657a9f..000000000
--- a/openfpga_flow/VerilogNetlists/ff_en.v
+++ /dev/null
@@ -1,40 +0,0 @@
-//-----------------------------------------------------
-// Design Name : D-type Flip-flop with Write Enable 
-// File Name   : ff_en.v
-// Function    : D flip-flop with asyn reset and set
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module DFF_EN (
-/* Global ports go first */
-input SET,     // set input
-input RST, // Reset input
-input WE, // Write Enable
-input CK, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q, // Q output
-output QB // QB output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge CK or posedge RST or posedge SET)
-if (RST) begin
-  q_reg <= 1'b0;
-end else if (SET) begin
-  q_reg <= 1'b1;
-end else if (WE) begin
-  q_reg <= D;
-end
-
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-assign Q = q_reg;
-assign QB = ~q_reg;
-`else
-assign Q = 1'bZ;
-assign QB = !Q;
-`endif
-
-endmodule //End Of Module