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[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol

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tangxifan 2021-06-07 17:58:00 -06:00
parent 9556f994b4
commit 54a53bc988
1 changed files with 14 additions and 10 deletions
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24
docs/source/manual/file_formats/fabric_bitstream.rst
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@ -43,21 +43,25 @@ The information depends on the type of configuration procotol.
.. option:: memory_bank
Multiple lines will be included, each of which is organized as <address><space><bits>.
Note that due to the use of Bit-Line and Word-Line decoders, every two lines are paired.
The first line represents the Bit-Line address and configuration bit.
The second line represents the Word-Line address and configuration bit.
Multiple lines will be included, each of which is organized as <bl_address><wl_address><bits>.
The size of address line and data input bits are shown as a comment in the bitstream file, which eases the development of bitstream downloader.
For example
.. code-block:: verilog
// Bitstream width (LSB -> MSB): <bl_address 5 bits><wl_address 5 bits><data input 1 bits>
The first part represents the Bit-Line address.
The second part represents the Word-Line address.
The third part represents the configuration bit.
For example
.. code-block:: xml
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address><wordline_address><bit_value>
<bitline_address><wordline_address><bit_value>
...
<bitline_address> <bit_value>
<wordline_address> <bit_value>
<bitline_address><wordline_address><bit_value>
.. note:: When there are multiple configuration regions, each ``<bit_value>`` may consist of multiple bits. For example, ``0110`` represents the bits for 4 configuration regions, where the 4 digits correspond to the bits from region ``0, 1, 2, 3`` respectively.