Merge pull request #767 from lnis-uofu/large_no_ts_test
Expand the no_time_stamp test case to bigger layout size
This commit is contained in:
tangxifan
GitHub
commit
5489f19bce
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@ -2,7 +2,7 @@
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# This script is designed to test the option --no_time_stamp in related commands
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# This script is designed to test the option --no_time_stamp in related commands
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# It can NOT be used an example script to achieve other objectives
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# It can NOT be used an example script to achieve other objectives
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#--write_rr_graph example_rr_graph.xml
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling route
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --clock_modeling route
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# Read OpenFPGA architecture definition
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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@ -60,7 +60,7 @@ report_bitstream_distribution --file ${OPENFPGA_OUTPUT_DIR}/bitstream_distributi
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# Write the Verilog netlist for FPGA fabric
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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# - Enable the use of explicit port mapping in Verilog netlist
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write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --verbose --no_time_stamp
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write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --include_timing --print_user_defined_template --use_relative_path --verbose --no_time_stamp
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# Write the Verilog testbench for FPGA fabric
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - We suggest the use of same output directory as fabric Verilog netlists
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@ -69,7 +69,7 @@ write_fabric_verilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --inc
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp
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write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ${OPENFPGA_OUTPUT_DIR} --explicit_port_mapping --no_time_stamp
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write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --no_time_stamp
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write_preconfigured_testbench --file ${OPENFPGA_OUTPUT_DIR} --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --use_relative_path --explicit_port_mapping --no_time_stamp
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# Write the SDC files for PnR backend
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# Write the SDC files for PnR backend
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# - Turn on every options here
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# - Turn on every options here
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@ -190,15 +190,16 @@ create-task _task_copy basic_tests/generate_fabric
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run-task _task_copy
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run-task _task_copy
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echo -e "Testing output files without time stamp";
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echo -e "Testing output files without time stamp";
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run-task basic_tests/no_time_stamp $@
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run-task basic_tests/no_time_stamp/device_1x1 $@
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run-task basic_tests/no_time_stamp/device_4x4 $@
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# Run git-diff to ensure no changes on the golden netlists
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# Run git-diff to ensure no changes on the golden netlists
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# Switch to root path in case users are running the tests in another location
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# Switch to root path in case users are running the tests in another location
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cd ${OPENFPGA_PATH}
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cd ${OPENFPGA_PATH}
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pwd
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pwd
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git config --global --add safe.directory ${OPENFPGA_PATH}
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git config --global --add safe.directory ${OPENFPGA_PATH}
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git log
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git log
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git diff --name-status -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'
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git diff --name-status -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/*/golden_outputs_no_time_stamp/**'
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if git diff --name-status --exit-code -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/**'; then
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if git diff --name-status --exit-code -- ':${OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/no_time_stamp/*/golden_outputs_no_time_stamp/**'; then
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echo -e "Golden netlist remain unchanged"
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echo -e "Golden netlist remain unchanged"
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else
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else
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echo -e "Detect changes in golden netlists"; exit 1;
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echo -e "Detect changes in golden netlists"; exit 1;
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@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout = auto
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openfpga_vpr_route_chan_width = 26
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openfpga_vpr_route_chan_width = 26
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openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
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openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
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@ -0,0 +1,16 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Netlist Summary
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ------ Include fabric top-level netlists -----
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`include "fabric_netlists.v"
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`include "and2_output_verilog.v"
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`include "and2_top_formal_verification.v"
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`include "and2_formal_random_top_tb.v"
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@ -0,0 +1,53 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: Fabric Netlist Summary
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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// ------ Include defines: preproc flags -----
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`include "fpga_defines.v"
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// ------ Include user-defined netlists -----
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`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
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`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
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// ------ Include primitive module netlists -----
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`include "sub_module/inv_buf_passgate.v"
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`include "sub_module/arch_encoder.v"
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`include "sub_module/local_encoder.v"
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`include "sub_module/mux_primitives.v"
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`include "sub_module/muxes.v"
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`include "sub_module/luts.v"
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`include "sub_module/wires.v"
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`include "sub_module/memories.v"
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`include "sub_module/shift_register_banks.v"
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// ------ Include logic block netlists -----
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`include "lb/logical_tile_io_mode_physical__iopad.v"
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`include "lb/logical_tile_io_mode_io_.v"
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`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
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`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
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`include "lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
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`include "lb/logical_tile_clb_mode_default__fle.v"
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`include "lb/logical_tile_clb_mode_clb_.v"
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`include "lb/grid_io_top.v"
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`include "lb/grid_io_right.v"
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`include "lb/grid_io_bottom.v"
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`include "lb/grid_io_left.v"
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`include "lb/grid_clb.v"
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// ------ Include routing module netlists -----
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`include "routing/sb_0__0_.v"
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`include "routing/sb_0__1_.v"
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`include "routing/sb_1__0_.v"
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`include "routing/sb_1__1_.v"
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`include "routing/cbx_1__0_.v"
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`include "routing/cbx_1__1_.v"
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`include "routing/cby_0__1_.v"
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`include "routing/cby_1__1_.v"
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// ------ Include fabric top-level netlists -----
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`include "fpga_top.v"
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@ -0,0 +1,36 @@
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# Configuration file for running experiments
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
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# Each job execute fpga_flow script on combination of architecture & benchmark
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# timeout_each_job is timeout for each job
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# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
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[GENERAL]
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run_engine=openfpga_shell
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power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
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power_analysis = true
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spice_output=false
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verilog_output=true
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timeout_each_job = 20*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
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openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
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openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
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openfpga_vpr_device_layout = 4x4
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openfpga_vpr_route_chan_width = 20
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openfpga_output_dir=${PATH:TASK_DIR}/golden_outputs_no_time_stamp
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[ARCHITECTURES]
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arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
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[BENCHMARKS]
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bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
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[SYNTHESIS_PARAM]
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bench_read_verilog_options_common = -nolatches
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bench0_top = and2
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[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
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@ -0,0 +1,126 @@
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//-------------------------------------------
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// FPGA Synthesizable Verilog Netlist
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// Description: FPGA Verilog Testbench for Formal Top-level netlist of Design: and2
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// Author: Xifan TANG
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// Organization: University of Utah
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//-------------------------------------------
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//----- Time scale -----
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`timescale 1ns / 1ps
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//----- Default net type -----
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`default_nettype none
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module and2_top_formal_verification_random_tb;
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// ----- Default clock port is added here since benchmark does not contain one -------
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reg [0:0] clk;
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// ----- Shared inputs -------
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reg [0:0] a;
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reg [0:0] b;
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// ----- FPGA fabric outputs -------
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wire [0:0] c_gfpga;
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// ----- Benchmark outputs -------
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wire [0:0] c_bench;
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// ----- Output vectors checking flags -------
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reg [0:0] c_flag;
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// ----- Error counter -------
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integer nb_error= 0;
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// ----- FPGA fabric instanciation -------
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and2_top_formal_verification FPGA_DUT(
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.a(a),
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.b(b),
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.c(c_gfpga)
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);
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// ----- End FPGA Fabric Instanication -------
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// ----- Reference Benchmark Instanication -------
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and2 REF_DUT(
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.a(a),
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.b(b),
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.c(c_bench)
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);
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// ----- End reference Benchmark Instanication -------
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// ----- Clock 'clk' Initialization -------
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initial begin
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clk[0] <= 1'b0;
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while(1) begin
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#0.4537859857
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clk[0] <= !clk[0];
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end
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end
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// ----- Begin reset signal generation -----
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// ----- End reset signal generation -----
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// ----- Input Initialization -------
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initial begin
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a <= 1'b0;
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b <= 1'b0;
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c_flag[0] <= 1'b0;
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end
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// ----- Input Stimulus -------
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always@(negedge clk[0]) begin
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a <= $random;
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b <= $random;
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end
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// ----- Begin checking output vectors -------
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// ----- Skip the first falling edge of clock, it is for initialization -------
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reg [0:0] sim_start;
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always@(negedge clk[0]) begin
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if (1'b1 == sim_start[0]) begin
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sim_start[0] <= ~sim_start[0];
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end else
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begin
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if(!(c_gfpga === c_bench) && !(c_bench === 1'bx)) begin
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c_flag <= 1'b1;
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end else begin
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c_flag<= 1'b0;
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end
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end
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end
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always@(posedge c_flag) begin
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if(c_flag) begin
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nb_error = nb_error + 1;
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$display("Mismatch on c_gfpga at time = %t", $realtime);
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|
end
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||||||
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end
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|
||||||
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||||||
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// ----- Begin output waveform to VCD file-------
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||||||
|
initial begin
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$dumpfile("and2_formal.vcd");
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$dumpvars(1, and2_top_formal_verification_random_tb);
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||||||
|
end
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// ----- END output waveform to VCD file -------
|
||||||
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|
||||||
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initial begin
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sim_start[0] <= 1'b1;
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$timeformat(-9, 2, "ns", 20);
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$display("Simulation start");
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// ----- Can be changed by the user for his/her need -------
|
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|
#6.353003979
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|
if(nb_error == 0) begin
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$display("Simulation Succeed");
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|
end else begin
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||||||
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$display("Simulation Failed with %d error(s)", nb_error);
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|
end
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$finish;
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|
end
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|
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endmodule
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||||||
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// ----- END Verilog module for and2_top_formal_verification_random_tb -----
|
||||||
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|
||||||
|
//----- Default net type -----
|
||||||
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`default_nettype none
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||||||
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|
||||||
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,16 @@
|
||||||
|
//-------------------------------------------
|
||||||
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// FPGA Synthesizable Verilog Netlist
|
||||||
|
// Description: Netlist Summary
|
||||||
|
// Author: Xifan TANG
|
||||||
|
// Organization: University of Utah
|
||||||
|
//-------------------------------------------
|
||||||
|
//----- Time scale -----
|
||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
// ------ Include fabric top-level netlists -----
|
||||||
|
`include "fabric_netlists.v"
|
||||||
|
|
||||||
|
`include "and2_output_verilog.v"
|
||||||
|
|
||||||
|
`include "and2_top_formal_verification.v"
|
||||||
|
`include "and2_formal_random_top_tb.v"
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,208 @@
|
||||||
|
<!--
|
||||||
|
- Report Bitstream Distribution
|
||||||
|
-->
|
||||||
|
|
||||||
|
<bitstream_distribution>
|
||||||
|
<regions>
|
||||||
|
<region id="0" number_of_bits="4210">
|
||||||
|
</region>
|
||||||
|
</regions>
|
||||||
|
<blocks>
|
||||||
|
<block name="fpga_top" number_of_bits="4210">
|
||||||
|
<block name="grid_clb_1__1_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_1__2_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_1__3_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_1__4_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_2__1_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_2__2_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_2__3_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_2__4_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_3__1_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_3__2_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_3__3_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_3__4_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_4__1_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_4__2_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_4__3_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_clb_4__4_" number_of_bits="136">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_top_1__5_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_top_2__5_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_top_3__5_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_top_4__5_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_right_5__4_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_right_5__3_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_right_5__2_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_right_5__1_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_bottom_4__0_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_bottom_3__0_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_bottom_2__0_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_bottom_1__0_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_left_0__1_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_left_0__2_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_left_0__3_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="grid_io_left_0__4_" number_of_bits="8">
|
||||||
|
</block>
|
||||||
|
<block name="sb_0__0_" number_of_bits="36">
|
||||||
|
</block>
|
||||||
|
<block name="sb_0__1_" number_of_bits="40">
|
||||||
|
</block>
|
||||||
|
<block name="sb_0__2_" number_of_bits="40">
|
||||||
|
</block>
|
||||||
|
<block name="sb_0__3_" number_of_bits="40">
|
||||||
|
</block>
|
||||||
|
<block name="sb_0__4_" number_of_bits="36">
|
||||||
|
</block>
|
||||||
|
<block name="sb_1__0_" number_of_bits="38">
|
||||||
|
</block>
|
||||||
|
<block name="sb_1__1_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_1__2_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_1__3_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_1__4_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_2__0_" number_of_bits="38">
|
||||||
|
</block>
|
||||||
|
<block name="sb_2__1_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_2__2_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_2__3_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_2__4_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_3__0_" number_of_bits="38">
|
||||||
|
</block>
|
||||||
|
<block name="sb_3__1_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_3__2_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_3__3_" number_of_bits="48">
|
||||||
|
</block>
|
||||||
|
<block name="sb_3__4_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_4__0_" number_of_bits="36">
|
||||||
|
</block>
|
||||||
|
<block name="sb_4__1_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_4__2_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_4__3_" number_of_bits="44">
|
||||||
|
</block>
|
||||||
|
<block name="sb_4__4_" number_of_bits="36">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_1__0_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_1__1_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_1__2_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_1__3_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_1__4_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_2__0_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_2__1_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_2__2_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_2__3_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_2__4_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_3__0_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_3__1_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_3__2_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_3__3_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_3__4_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_4__0_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_4__1_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_4__2_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_4__3_" number_of_bits="16">
|
||||||
|
</block>
|
||||||
|
<block name="cbx_4__4_" number_of_bits="32">
|
||||||
|
</block>
|
||||||
|
<block name="cby_0__1_" number_of_bits="29">
|
||||||
|
</block>
|
||||||
|
<block name="cby_0__2_" number_of_bits="29">
|
||||||
|
</block>
|
||||||
|
<block name="cby_0__3_" number_of_bits="29">
|
||||||
|
</block>
|
||||||
|
<block name="cby_0__4_" number_of_bits="29">
|
||||||
|
</block>
|
||||||
|
<block name="cby_1__1_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_1__2_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_1__3_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_1__4_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_2__1_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_2__2_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_2__3_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_2__4_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_3__1_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_3__2_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_3__3_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_3__4_" number_of_bits="12">
|
||||||
|
</block>
|
||||||
|
<block name="cby_4__1_" number_of_bits="31">
|
||||||
|
</block>
|
||||||
|
<block name="cby_4__2_" number_of_bits="31">
|
||||||
|
</block>
|
||||||
|
<block name="cby_4__3_" number_of_bits="31">
|
||||||
|
</block>
|
||||||
|
<block name="cby_4__4_" number_of_bits="31">
|
||||||
|
</block>
|
||||||
|
</block>
|
||||||
|
</blocks>
|
||||||
|
</bitstream_distribution>
|
||||||
|
|
@ -0,0 +1,75 @@
|
||||||
|
#############################################
|
||||||
|
# Synopsys Design Constraints (SDC)
|
||||||
|
# For FPGA fabric
|
||||||
|
# Description: Constrain timing of Connection Block cbx_1__0_ for PnR
|
||||||
|
# Author: Xifan TANG
|
||||||
|
# Organization: University of Utah
|
||||||
|
#############################################
|
||||||
|
|
||||||
|
#############################################
|
||||||
|
# Define time unit
|
||||||
|
#############################################
|
||||||
|
set_units -time s
|
||||||
|
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/chanx_left_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/chanx_right_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/chanx_left_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/chanx_right_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/chanx_left_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/chanx_right_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/chanx_left_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/chanx_right_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/chanx_left_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/chanx_right_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/chanx_left_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/chanx_right_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/chanx_left_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/chanx_right_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/chanx_left_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/chanx_right_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/chanx_left_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/chanx_right_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/chanx_left_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/chanx_right_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[1] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[6] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[2] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[7] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[3] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[8] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[4] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[9] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[0] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_left_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__0_/chanx_right_in[5] -to fpga_top/cbx_1__0_/bottom_grid_top_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
|
@ -0,0 +1,53 @@
|
||||||
|
#############################################
|
||||||
|
# Synopsys Design Constraints (SDC)
|
||||||
|
# For FPGA fabric
|
||||||
|
# Description: Constrain timing of Connection Block cbx_1__1_ for PnR
|
||||||
|
# Author: Xifan TANG
|
||||||
|
# Organization: University of Utah
|
||||||
|
#############################################
|
||||||
|
|
||||||
|
#############################################
|
||||||
|
# Define time unit
|
||||||
|
#############################################
|
||||||
|
set_units -time s
|
||||||
|
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/chanx_left_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/chanx_right_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/chanx_left_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/chanx_right_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/chanx_left_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/chanx_right_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/chanx_left_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/chanx_right_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/chanx_left_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/chanx_right_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/chanx_left_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/chanx_right_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[6] -to fpga_top/cbx_1__1_/chanx_left_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[6] -to fpga_top/cbx_1__1_/chanx_right_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/chanx_left_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/chanx_right_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/chanx_left_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/chanx_right_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/chanx_left_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/chanx_right_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[0] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_2_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[1] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_I_6_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[2] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[7] -to fpga_top/cbx_1__1_/top_grid_bottom_width_0_height_0_subtile_0__pin_clk_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[3] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[8] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[4] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[4] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[9] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_left_in[5] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__1_/chanx_right_in[5] -to fpga_top/cbx_1__1_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||||
|
|
@ -0,0 +1,75 @@
|
||||||
|
#############################################
|
||||||
|
# Synopsys Design Constraints (SDC)
|
||||||
|
# For FPGA fabric
|
||||||
|
# Description: Constrain timing of Connection Block cbx_1__4_ for PnR
|
||||||
|
# Author: Xifan TANG
|
||||||
|
# Organization: University of Utah
|
||||||
|
#############################################
|
||||||
|
|
||||||
|
#############################################
|
||||||
|
# Define time unit
|
||||||
|
#############################################
|
||||||
|
set_units -time s
|
||||||
|
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[0] -to fpga_top/cbx_1__4_/chanx_left_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[0] -to fpga_top/cbx_1__4_/chanx_right_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[1] -to fpga_top/cbx_1__4_/chanx_left_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[1] -to fpga_top/cbx_1__4_/chanx_right_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[2] -to fpga_top/cbx_1__4_/chanx_left_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[2] -to fpga_top/cbx_1__4_/chanx_right_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[3] -to fpga_top/cbx_1__4_/chanx_left_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[3] -to fpga_top/cbx_1__4_/chanx_right_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[4] -to fpga_top/cbx_1__4_/chanx_left_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[4] -to fpga_top/cbx_1__4_/chanx_right_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[5] -to fpga_top/cbx_1__4_/chanx_left_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[5] -to fpga_top/cbx_1__4_/chanx_right_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[6] -to fpga_top/cbx_1__4_/chanx_left_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[6] -to fpga_top/cbx_1__4_/chanx_right_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[7] -to fpga_top/cbx_1__4_/chanx_left_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[7] -to fpga_top/cbx_1__4_/chanx_right_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[8] -to fpga_top/cbx_1__4_/chanx_left_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[8] -to fpga_top/cbx_1__4_/chanx_right_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[9] -to fpga_top/cbx_1__4_/chanx_left_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[9] -to fpga_top/cbx_1__4_/chanx_right_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[0] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[0] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[5] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[5] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[1] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[1] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[6] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[6] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[2] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[2] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[7] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[7] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[3] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[3] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[8] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[8] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[4] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[4] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[9] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[9] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[0] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[0] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[5] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[5] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[1] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[1] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[6] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[6] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[2] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[2] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[7] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[7] -to fpga_top/cbx_1__4_/top_grid_bottom_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[3] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[3] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[8] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[8] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[4] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[4] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[9] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[9] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_4_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_left_in[0] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cbx_1__4_/chanx_right_in[0] -to fpga_top/cbx_1__4_/bottom_grid_top_width_0_height_0_subtile_0__pin_I_8_[0] 7.247000222e-11
|
||||||
|
|
@ -0,0 +1,71 @@
|
||||||
|
#############################################
|
||||||
|
# Synopsys Design Constraints (SDC)
|
||||||
|
# For FPGA fabric
|
||||||
|
# Description: Constrain timing of Connection Block cby_0__1_ for PnR
|
||||||
|
# Author: Xifan TANG
|
||||||
|
# Organization: University of Utah
|
||||||
|
#############################################
|
||||||
|
|
||||||
|
#############################################
|
||||||
|
# Define time unit
|
||||||
|
#############################################
|
||||||
|
set_units -time s
|
||||||
|
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/chany_bottom_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/chany_top_out[0] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/chany_bottom_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/chany_top_out[1] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/chany_bottom_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/chany_top_out[2] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/chany_bottom_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/chany_top_out[3] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/chany_bottom_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/chany_top_out[4] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/chany_bottom_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/chany_top_out[5] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/chany_bottom_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/chany_top_out[6] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/chany_bottom_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/chany_top_out[7] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/chany_bottom_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/chany_top_out[8] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/chany_bottom_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/chany_top_out[9] 2.272500113e-12
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_3_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/right_grid_left_width_0_height_0_subtile_0__pin_I_7_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_0__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_1__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_2__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[0] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[5] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_3__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[1] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[6] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_4__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[2] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[7] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_5__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[3] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[8] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_6__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[4] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_bottom_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
|
set_max_delay -from fpga_top/cby_0__1_/chany_top_in[9] -to fpga_top/cby_0__1_/left_grid_right_width_0_height_0_subtile_7__pin_outpad_0_[0] 7.247000222e-11
|
||||||
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Reference in New Issue