From 02e21d115b318dc3423ba87ebe93a9cceed7fddd Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 10:00:12 -0600 Subject: [PATCH 1/5] [Documentation] Update 3-rd party tool version requirements --- docs/source/tutorials/tools.rst | 48 +++++++++++++++++---------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/docs/source/tutorials/tools.rst b/docs/source/tutorials/tools.rst index 0d22041d3..c332d602a 100644 --- a/docs/source/tutorials/tools.rst +++ b/docs/source/tutorials/tools.rst @@ -22,26 +22,28 @@ Third-Party Tools OpenFPGA accepts and outputs in standard file formats, and therefore can interface a wide range of commercial and open-source tools. -+--------------+-------------------------+ -| Usage | Tools | -+==============+=========================+ -| Backend | Synopsys IC Compiler II | -| | | -| | Cadence Innovus | -+--------------+-------------------------+ -| Timing | Synopsys PrimeTime | -| Analyzer | | -| | Cadence Tempus | -+--------------+-------------------------+ -| Verification | Synopsys VCS | -| | | -| | Synopsys Formality | -| | | -| | Mentor ModelSim | -| | | -| | Mentor QuestaSim | -| | | -| | Cadence NCSim | -| | | -| | Icarus iVerilog | -+--------------+-------------------------+ ++--------------+-------------------------+---------------------+ +| Usage | Tools | Version Requirement | ++==============+=========================+=====================+ +| Backend | Synopsys IC Compiler II | v2019.03 or later | +| | | | +| | Cadence Innovus | v19.1 or later | ++--------------+-------------------------+---------------------+ +| Timing | Synopsys PrimeTime | v2019.03 or later | +| Analyzer | | | +| | Cadence Tempus | v19.15 or later | ++--------------+-------------------------+---------------------+ +| Verification | Synopsys VCS | v2019.06 or later | +| | | | +| | Synopsys Formality | v2019.03 or later | +| | | | +| | Mentor ModelSim | v10.6 or later | +| | | | +| | Mentor QuestaSim | v2019.3 or later | +| | | | +| | Cadence NCSim | v15.2 or later | +| | | | +| | Icarus iVerilog | v10.1 or later | ++--------------+-------------------------+---------------------+ + +* The version requirements is based on our local tests. Older versions may work. From 113708c68f0b1ed408fd0f41c0b7365c9f943057 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 11:56:10 -0600 Subject: [PATCH 2/5] [Documentation] Reorganization the overview part by adding technical highlights --- docs/source/index.rst | 5 +- docs/source/manual/fpga_verilog/testbench.rst | 10 ++ .../openfpga_shell/launch_openfpga_shell.rst | 2 - .../{ => overview}/figures/OpenFPGA_logo.pdf | Bin .../{ => overview}/figures/OpenFPGA_logo.png | Bin .../figures/fpga_sdc_motivation.png | Bin .../figures/fpga_verilog_motivation.png | Bin .../figures/openfpga_arch_lang_coverage.png | Bin .../{ => overview}/figures/openfpga_flow.png | Bin .../figures/openfpga_motivation.png | Bin docs/source/overview/index.rst | 9 ++ docs/source/{ => overview}/motivation.rst | 0 docs/source/overview/tech_highlights.rst | 90 ++++++++++++++++++ 13 files changed, 112 insertions(+), 4 deletions(-) rename docs/source/{ => overview}/figures/OpenFPGA_logo.pdf (100%) rename docs/source/{ => overview}/figures/OpenFPGA_logo.png (100%) rename docs/source/{ => overview}/figures/fpga_sdc_motivation.png (100%) rename docs/source/{ => overview}/figures/fpga_verilog_motivation.png (100%) rename docs/source/{ => overview}/figures/openfpga_arch_lang_coverage.png (100%) rename docs/source/{ => overview}/figures/openfpga_flow.png (100%) rename docs/source/{ => overview}/figures/openfpga_motivation.png (100%) create mode 100644 docs/source/overview/index.rst rename docs/source/{ => overview}/motivation.rst (100%) create mode 100644 docs/source/overview/tech_highlights.rst diff --git a/docs/source/index.rst b/docs/source/index.rst index 9a317c924..f507a8c54 100644 --- a/docs/source/index.rst +++ b/docs/source/index.rst @@ -7,9 +7,10 @@ Welcome to OpenFPGA's documentation! ==================================== .. toctree:: - :caption: Motivation + :maxdepth: 2 + :caption: Overview - motivation + overview/index .. toctree:: :maxdepth: 2 diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index 1be9ec688..dfdb22e8e 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -5,6 +5,16 @@ Testbench In this part, we will introduce the hierarchy, dependency and functionality of each Verilog testbench, which are generated to verify a FPGA fabric implemented with an application. ++-----------------+---------+----------------+---------------+ +| Testbench Type | Runtime | Test Vector | Test Coverage | ++=================+=========+================+===============+ +| Full | Long | Random Stimuli | Full fabric | ++-----------------+---------+----------------+---------------+ +| Formal-oriented | Short | Random Stimuli | Programmable | +| | | or | fabric only | +| | | Formal Method | | ++-----------------+---------+----------------+---------------+ + OpenFPGA can auto-generate two types of Verilog testbenches to validate the correctness of the fabric: full and formal-oriented. Both testbenches share the same organization, as depicted in :numref:`fig_verilog_testbench_organization` (a). To enable self-testing, the FPGA and user's RTL design (simulate using an HDL simulator) are driven by the same input stimuli, and any mismatch on their outputs will raise an error flag. diff --git a/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst index 8ef7e3858..3ef6e9fb5 100644 --- a/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst +++ b/docs/source/manual/openfpga_shell/launch_openfpga_shell.rst @@ -11,8 +11,6 @@ To launch OpenFPGA shell, users can choose two modes. Launch OpenFPGA in interactive mode where users type-in command by command and get runtime results - .. warning:: Currently OpenFPGA does not support continued lines and comments - .. option:: --file or -f Launch OpenFPGA in script mode where users write commands in scripts and FPGA will execute them diff --git a/docs/source/figures/OpenFPGA_logo.pdf b/docs/source/overview/figures/OpenFPGA_logo.pdf similarity index 100% rename from docs/source/figures/OpenFPGA_logo.pdf rename to docs/source/overview/figures/OpenFPGA_logo.pdf diff --git a/docs/source/figures/OpenFPGA_logo.png b/docs/source/overview/figures/OpenFPGA_logo.png similarity index 100% rename from docs/source/figures/OpenFPGA_logo.png rename to docs/source/overview/figures/OpenFPGA_logo.png diff --git a/docs/source/figures/fpga_sdc_motivation.png b/docs/source/overview/figures/fpga_sdc_motivation.png similarity index 100% rename from docs/source/figures/fpga_sdc_motivation.png rename to docs/source/overview/figures/fpga_sdc_motivation.png diff --git a/docs/source/figures/fpga_verilog_motivation.png b/docs/source/overview/figures/fpga_verilog_motivation.png similarity index 100% rename from docs/source/figures/fpga_verilog_motivation.png rename to docs/source/overview/figures/fpga_verilog_motivation.png diff --git a/docs/source/figures/openfpga_arch_lang_coverage.png b/docs/source/overview/figures/openfpga_arch_lang_coverage.png similarity index 100% rename from docs/source/figures/openfpga_arch_lang_coverage.png rename to docs/source/overview/figures/openfpga_arch_lang_coverage.png diff --git a/docs/source/figures/openfpga_flow.png b/docs/source/overview/figures/openfpga_flow.png similarity index 100% rename from docs/source/figures/openfpga_flow.png rename to docs/source/overview/figures/openfpga_flow.png diff --git a/docs/source/figures/openfpga_motivation.png b/docs/source/overview/figures/openfpga_motivation.png similarity index 100% rename from docs/source/figures/openfpga_motivation.png rename to docs/source/overview/figures/openfpga_motivation.png diff --git a/docs/source/overview/index.rst b/docs/source/overview/index.rst new file mode 100644 index 000000000..32b8fa75f --- /dev/null +++ b/docs/source/overview/index.rst @@ -0,0 +1,9 @@ +.. _overview: + Overview + +.. toctree:: + :maxdepth: 2 + + motivation + + tech_highlights diff --git a/docs/source/motivation.rst b/docs/source/overview/motivation.rst similarity index 100% rename from docs/source/motivation.rst rename to docs/source/overview/motivation.rst diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst new file mode 100644 index 000000000..8ec322b67 --- /dev/null +++ b/docs/source/overview/tech_highlights.rst @@ -0,0 +1,90 @@ +Technical Highlights +-------------------- + +The follow lists of technical features are created to help users spot their needs in customizing FPGA fabrics.(**as of October 2020**) + +Supported Circuit Designs +~~~~~~~~~~~~~~~~~~~~~~~~~ + ++---------------+-----------------+--------------+-------------------------+ +| Circuit Types | Auto-generation | User-Defined | Design Topologies | ++===============+=================+==============+=========================+ +| Inverter | Yes | Yes | - Power-gating | ++---------------+-----------------+--------------+-------------------------+ +| Buffer | Yes | Yes | - Tapered buffers | +| | | | - Power-gating | ++---------------+-----------------+--------------+-------------------------+ +| AND gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| OR gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| MUX2 gate | Yes | Yes | - 2-input | ++---------------+-----------------+--------------+-------------------------+ +| Pass gate | Yes | Yes | - Transmission gate | +| | | | - Pass transistor | ++---------------+-----------------+--------------+-------------------------+ +| Look-Up Table | Yes | Yes | - **Any size** | +| | | | - Single-output LUT | +| | | | - Fracturable LUT | +| | | | - Buffer location | ++---------------+-----------------+--------------+-------------------------+ +| Routing | Yes | No | - **Any size** | +| Multiplexer | | | - Buffer location | +| | | | - One-level structure | +| | | | - Treee structure | +| | | | - Multi-level structure | +| | | | - Local encoders | +| | | | - Constant inputs | ++---------------+-----------------+--------------+-------------------------+ +| Configurable | No | Yes | - Latch | +| Memory | | | - SRAM | +| | | | - D-type flip-flop | ++---------------+-----------------+--------------+-------------------------+ +| Block RAM | No | Yes | - Single-port | +| | | | - Dual-port | +| | | | - Fracturable | +| | | | - **Any size** | ++---------------+-----------------+--------------+-------------------------+ +| Arithmetic | No | Yes | - **Any size** | +| Units | | | - Multiplier | +| | | | - Adder | ++---------------+-----------------+--------------+-------------------------+ +| I/O | No | Yes | - General purpose I/O | +| | | | - Bi-directional buffer | +| | | | - AIB | ++---------------+-----------------+--------------+-------------------------+ + + +* The user defined netlist could come from a standard cell + +Supported FPGA Architectures +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +We support most FPGA architectures that VPR can support! +The following are most commonly seen architectural features: + ++--------------------+----------------------------------------------+ +| Block Type | Architecture features | ++====================+==============================================+ +| Programmable Block | - Single-mode Configurable Logic Block (CLB) | +| | - Multi-mode Configurable Logic Block (CLB) | +| | - Single-mode heterogeneous blocks | +| | - Multi-mode heterogeneous blocks | +| | - Flexible local routing architecture | ++--------------------+----------------------------------------------+ +| Routing Block | - Tileable routing architecture | +| | - Flexible connectivity | +| | - Flexible Switch Block Patterns | ++--------------------+----------------------------------------------+ + +Supported Verilog Modeling +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +OpenFPGA supports the following Verilog features in auto-generated netlists for circuit designs + +- Synthesizable Behavioral Verilog + +- Structural Verilog + +- Implicit/Explicit port mapping + From c8339fc47393b3702ae0abbfd01710dd918a66a5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:00:30 -0600 Subject: [PATCH 3/5] [Documentation] Typo fix --- docs/source/overview/tech_highlights.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index 8ec322b67..f3b04b37a 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -31,7 +31,7 @@ Supported Circuit Designs | Routing | Yes | No | - **Any size** | | Multiplexer | | | - Buffer location | | | | | - One-level structure | -| | | | - Treee structure | +| | | | - Tree structure | | | | | - Multi-level structure | | | | | - Local encoders | | | | | - Constant inputs | From 56ab63d93915b2f48967de7ab634953ebc2dbd96 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:02:15 -0600 Subject: [PATCH 4/5] [Documentation] Fix format in table --- docs/source/manual/fpga_verilog/testbench.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst index dfdb22e8e..db3ed8835 100644 --- a/docs/source/manual/fpga_verilog/testbench.rst +++ b/docs/source/manual/fpga_verilog/testbench.rst @@ -11,7 +11,7 @@ In this part, we will introduce the hierarchy, dependency and functionality of e | Full | Long | Random Stimuli | Full fabric | +-----------------+---------+----------------+---------------+ | Formal-oriented | Short | Random Stimuli | Programmable | -| | | or | fabric only | +| | | | fabric only | | | | Formal Method | | +-----------------+---------+----------------+---------------+ From 800931c8400dc5291899a0a7c0d4ae08bcd0466d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 6 Oct 2020 12:16:15 -0600 Subject: [PATCH 5/5] [Documentation] Add configuration protocol to technical highlights --- docs/source/overview/tech_highlights.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/source/overview/tech_highlights.rst b/docs/source/overview/tech_highlights.rst index f3b04b37a..f4a915da6 100644 --- a/docs/source/overview/tech_highlights.rst +++ b/docs/source/overview/tech_highlights.rst @@ -76,6 +76,11 @@ The following are most commonly seen architectural features: | | - Flexible connectivity | | | - Flexible Switch Block Patterns | +--------------------+----------------------------------------------+ +| Configuration | - Chain-based organization | +| Protocol | - Frame-based organization | +| | - Memory bank organization | +| | - Flatten organization | ++--------------------+----------------------------------------------+ Supported Verilog Modeling ~~~~~~~~~~~~~~~~~~~~~~~~~~